Wouter Polspoel

Composition influence on the physical and electrical properties of SrxTi1−xOy-based metal-insulator-metal capacitors prepared by atomic layer deposition using TiN bottom electrodes

In this work, the physical and electrical properties of SrxTi1−xOy (STO)-based metal-insulator-metal capacitors (MIMcaps) with various compositions are studied in detail. While most recent studies on STO were done on noblelike metal electrodes (Ru, Pt), this work focuses on a low temperature (250 °C) atomic layer deposition (ALD) process, using an alternative precursor set and carefully optimized processing conditions, enabling the use of low-cost, manufacturable-friendly TiN electrodes. Physical analyses show that the film crystallization temperature, its texture and morphology strongly depends on the Sr/Ti ratio. Such physical variations have a direct impact on the electric properties of SrxTi1−xOy based capacitors. It is found that Sr-enrichment result in a monotonous decrease in the dielectric constant and leakage current as predicted by ab initio calculations. The intercept of the EOT vs physical thickness plot further indicates that increasing the Sr-content at the film interface with the bottom TiN...

Conductive atomic force microscopy studies of thin SiO2 layer degradation

The dielectric degradation of ultrathin (∼2nm) silicon dioxide (SiO2) layers has been investigated by constant and ramped voltage stresses with the conductive atomic force microscopy (CAFM). CAFM imaging shows clearly the lateral degradation propagation and its saturation. Current-voltage characteristics, performed at nanometer scale, show the trap creation rate in function of the stress condition. The critical trap density has been found.

Impact of crystallization behavior of SrxTiyOz films on electrical properties of metal-insulator-metal capacitors with TiN electrodes

Metastable perovskite SrxTiyOz (STO) films were formed over a wide composition range by crystallization of layers grown by atomic layer deposition. An expansion of the lattice, decrease in permittivity and mild increase in band gap are observed with increasing Sr content. Sr-rich films [Sr/(Sr+Ti)∼62 at. %] show significant improvement in leakage current at low equivalent oxide thicknesses (EOT) as compared to stoichiometric films (Sr/(Sr+Ti) ∼50 at. %). TiN/STO/TiN capacitors with leakage ∼10−6 A/cm2 at 1 V were obtained at 0.6 nm EOT for crystalline Sr-rich STO. The difference in leakage behavior was found to correlate with different microstructures developed during crystallization.

Experimental studies of dose retention and activation in fin field-effect-transistor-based structures

With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extracting the quantitative active carrier concentration in the fins.With emerging three-dimensional device architectures for advanced silicon devices such as fin field-effect-transistors (FinFETs), new metrology challenges are faced to characterize dopants. The ratio of dopant concentration in the top surface and sidewalls of FinFETs may differ significantly, thereby influencing the performance of these devices. In this work, a methodology involving secondary ion mass spectrometry (SIMS) is presented to study the dose conformality in fins. However, SIMS is limited to probe the quantitative chemical dopant concentration (i.e., top/sidewall of fins). The fraction of the active dopant concentration determining the performance of FinFETs would still be unknown. Additionally, the concept based on SIMS is unable to provide information on the lateral junction depth. Thus, to obtain the unknown active dopant concentration and their spatial distribution, the authors extend their study by measuring the cross section of the fins with scanning spreading resistance microscopy and extr...

Physical degradation of gate dielectrics induced by local electrical stress using conductive atomic force microscopy

Local electrical stress in gate dielectrics using conductive atomic force microscopy (C-AFM) induces structural damage in these layers. To allow C-AFM to become a mature technique to study oxide degradation, the impact of this structural damage, i.e., protrusions and holes, on the electrical behavior must be well understood. The physical nature and growth mechanism of protrusions due to a negative substrate voltage (Vs<0) is, however, debated in literature. In this work, we have studied the chemical composition of the surface protrusions using various analysis techniques (atomic force microscopy, transmission electron microscopy, and electron energy loss spectroscopy) showing that it consists of oxidized Si. A mechanism is proposed to explain the correlation between the observed surface damage and the measured current during constant voltage stress.

High-k Dielectrics and Metal Gates for Future Generation Memory Devices

The requirements and development of high-k dielectric films for application in storage cells of future generation flash and Dynamic Random Access Memory (DRAM) devices are reviewed. Dielectrics with k-value in the 9-30 range are studied as insulators between charge storage layers and control gates in flash devices. For this application, large band gaps (> 6 eV) and band offsets are required, as well as low trap densities. Materials studied include aluminates and scandates. For DRAM metal-insulator-metal (MIM) capacitors, aggressive scaling of the equivalent oxide thickness (with targets down to 0.3 nm) drives the research towards dielectrics with k-values > 50. Due to the high aspect ratio of MIMCap structures, highly conformal deposition techniques are needed, triggering a substantial effort to develop Atomic Layer Deposition (ALD) processes for the deposition of metal gates and high-k dielectrics. Materials studied include Sr and Ba-based perovskites, with SrTiO3 as one of the most promising candidates, as well as tantalates, titanates and niobates.

Bipolar Switching Characteristics and Scalability in NiO Layers Made by Thermal Oxidation of Ni

This paper deals with the bipolar switching properties of Ni\NiO\Ni cells for which the NiO layer is made by thermal oxidation of Ni layers. Physical characterization of the NiO layer revealed a strong deficiency in oxygen and a defective crystal structure. This microstructure allowed reproducible bipolar switching, which we attributed to the drift of oxygen anionic species and redox reactions at the anode. Conductive atomic force microscopy (C-AFM) experiments on Ni\NiO surfaces showed the scaling potential of the bipolar switching. C-AFM and macroscopic electrical measurements showed similarities and consistent results related to oxygen movement effects at the nanometer scale through relaxation processes and switching events. A discussion is conducted on the origin of the change in resistance, observed either at a microscopic or at a macroscopic scale. A distinction is made between electrochemical redox reactions taking place along conductive channels near the Ni\NiO\Ni top electrode and local changes of oxygen-vacancy densities.

0.5 nm EOT low leakage ALD SrTiO 3 on TiN MIM capacitors for DRAM applications

We demonstrate for the first time record low Leakage-EOT (3.5 times 10-7 A/cm2 at 1V, EOT=0.49 nm) MIM capacitors fabricated using a low temperature (250degC) ALD SrTiO3 (STO) deposition process on ALD TiN bottom electrode. While most previous work on STO used deposition techniques not compatible with high aspect ratio DRAM applications, recent work on ALD STO showed promise on noble-like metal electrodes (Ru, Pt) [1,2]. In this work, a low temperature ALD process with alternative precursor set and carefully optimized deposition and processing conditions enables the use of low-cost, manufacturable-friendly TiN electrode MIMcaps for future DRAM nodes. Composition (Sr-rich) and process optimization allowed minimization of interfacial EOT penalties and leakage reduction by decreasing the density of leakier STO grains.

Influence of vacuum environment on conductive atomic force microscopy measurements of advanced metal-oxide-semiconductor gate dielectrics

Most of the knowledge about the electrical behavior of gate dielectric materials has been gained from measurements performed on macroscopic metal-oxide-semiconductor MOS capacitors or transistors using standard electrical characterization methods at wafer level. Although very important information has been obtained using these methods, they provide spatially averaged information on the electrical properties of the material. On the contrary, conductive atomic force microscopy CAFM allows us to characterize topographically and electrically the gate dielectric with nanometer resolution. The CAFM works on bare gate dielectric surfaces and the CAFM tip plays the role of the metal electrode of a nanometer sized MOS capacitor with an area of few hundreds of nm2. Therefore, these measurements allow us to study the spatial distribution of current throughout the device area and its dependence on the applied voltage. To grant the current flow between the tip and the sample, the CAFM must work in contact mode. Due to that, when scanning in air with the CAFM, some undetermined reaction occurs between the tip and the sample probably related to water and/or hydrocarbons , which can cause loss of conductivity and CAFM resolution. In addition, when carriers are injected from the tip, local anodic oxidation is triggered. All these effects are even worse for high-k devices. To avoid these problems, one possibility could be measuring in con-

Comparison of standard macroscopic and conductive atomic force microscopy leakage measurements on gate removed high-k capacitors

Understanding the origin and mechanism of detrimental local phenomena such as charge trapping, trap assisted tunneling, and breakdown in high-k gate oxides adds to the improvement of refining the layer deposition process. Conductive atomic force microscopy (AFM) is a relatively new technique that is able to visualize these local phenomena. In this work we improve the quality of the comparison between standard macroscopic and conductive AFM (C-AFM) microscopic gate leakage measurements by enabling measurements on the exact same dielectric layers of metal gate high-k capacitors and transistors, using a well tuned gate wet etch process. An agreement in leakage current between both measurement types is obtained. Furthermore, we visualize with C-AFM the location and current magnitude of breakdown spots which were induced by standard macroscopic electrical stress. The ability of investigating the local leakage behavior of real devices as it is shown in this work opens the way to better understand gate leakage m...