Ole Lühn

Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV

In this paper, the effect of annealing condition on the microstructural and mechanical behavior of copper through-silicon via (Cu-TSV) is studied. The hardness of Cu-TSV scaled with the Hall–Petch relation, with the average hardness values of 1.9 GPa, 2.2 GPa and 2.3–2.8 GPa, respectively for the annealed, room temperature (RT) aged and the as-deposited samples. The increase in hardness toward the top of the as-deposited sample is related to the decrease in grain size. The annealed and the as-deposited samples showed a constant elastic modulus (E-modulus) value across the length of Cu-TSV of 140 GPa and 125 GPa respectively, while the RT aged sample showed a degradation in E-modulus from the bottom of the TSV (140 GPa) to the top (110 GPa). These differences in E-modulus values and trends under the different test conditions were found to be unrelated with the crystallographic texture of the samples, but could be related to the presence of residual stresses. No correlation is found between the hardness and E-modulus data. This is attributed to the coupling and competitive effects of grain size and residual stresses, with the grain size effect having a dominant influence on hardness, while the presence of residual stresses dominated the E-modulus result.

Scalable Through Silicon Via with polymer deep trench isolation for 3D wafer level packaging

A scalable generic Through Silicon Via (TSV) process is developed using spin-on dielectric polymer as isolation layer where deep annular trenches in Silicon are filled with the polymer. Following parameters are found to be affecting the polymer material spreading on the wafer surface and the filling performance: pre-treatments on the wafer surface, TSV density and physical properties of the polymer. Yielding TSV chains are measured on the fabricated wafers and the TSV resistance is found to be ≪100mΩ. It is a via-last TSV process which is applicable to any silicon technology.

Changing Superfilling Mode for Copper Electrodeposition in Blind Holes from Differential Inhibition to Differential Acceleration

Blind holes 5 μm diam and 25 μm in depth were filled with electrodeposited copper. Before electrodeposition, the blind holes were fully metallized with a copper seed layer or with a thin sputtered Ta layer deposited on top of the copper seed layer. Filling of partially Ta-capped features was three times faster than filling fully metallized features. For fully metallized features, the growth mode for copper electrodeposition is dominated by diffusion adsorption of a leveling agent. For partially Ta-capped surfaces, the growth mode was modified to differential acceleration through accumulation of an accelerating species at the bottom of features.

Development of vertical and tapered via etch for 3D through wafer interconnect technology

Two types of dry silicon etch techniques are developed to cover two different areas of demand for interconnect technology: one for high aspect ratio (AR) vertical vias and one for tapered vias. Various sizes of vertical vias and trenches with diameters/widths ranging from 1-100 mum with an AR up to 50 are realized using Bosch deep reactive ion etch (DRIE) process. A linear model is applied to describe and to give physical insight in the aspect ratio dependant etch (ARDE) effect. The feasibility of the vertical vias as electrical interconnect is shown by isolating them from the substrate by silicon oxide and then filling with polysilicon. The tapered vias are typically post-processed on fabricated device wafers, making it inherently a more generic approach where diameter size can be large and low AR can be tolerated. Vias with a depth of ~100 mum and a diameter of ~50mum at the bottom (though larger at top) are realized. Varying various etch parameters, slope angles of 70deg-80deg are realized to allow for conformal deposition of dielectric/seed materials on the sidewalls and to allow lithography within the via. Reactive ion etch (RIE) is used to fabricate sloped vias by simultaneously applying etch and passivation gasses. Negative angles on the via top and sidewall roughness are observed that introduce conformal coating problems and increased leakage currents. Smoothening techniques using maskless wet and dry silicon etching are investigated to overcome these problems.

Monitoring the Superfilling of Blind Holes with Electrodeposited Copper

Blind holes 5 μm in diameter and 25 μm deep were filled with copper electrodeposited from a copper sulfate electrolyte containing chloride ions, a suppressor, and an accelerator. A thin tantalum layer was deposited on top of a copper seed layer to locally inhibit the subsequent electrodeposition of copper. A clear difference appeared in the evolution of the cathode potential recorded during the galvanostatic deposition of copper on either copper metallized flat substrates or substrates containing copper metallized recessed blind holes and selectively coated with Ta at the outside. The different steps during the filling of blind holes by electrolytic copper were monitored and analyzed based on the evolution of the cathode potential during electrodeposition. An electrochemical depolarization of the electrode surface induced by an accelerating species occurred first. The subsequent evolution of the potential was dominated by a change in the electrode surface that occurs during the superfilling of blind holes with copper. Finally, the time to achieve a complete filling of blind holes with electrolytic copper was determined. A deeper insight on the superfilling mechanism with electrodeposited copper was obtained.

Reducing the electrodeposition time for filling microvias with copper for 3D technology

We present two approaches to reduce the process time needed for filling vias of 5 mum diameter and 25 mum depth with copper by electrodeposition. In the first approach, the effect of model additives on the filling of vias with electroplated copper was investigated as well as the influence of the applied current density on the filling process. The variation of the concentration of leveler and accelerator additives was investigated. Their influence on the void-free filling of such vias was determined. A high leveler concentration allowed to achieve a void-free fill. The copper deposited on the top surface was in the range of 2.5 mum. The filling was completed within 45 minutes. The filling time could even be further reduced to 25 minutes by introducing a waveform with two galvanostatic steps. The second approach demonstrates void-free via filling with copper electrodeposition at the top of the wafer surface blocked with self-assembled monolayers of octadecanethiol. With thin Ta-films deposited at the top surface before electrodeposition is started, almost no copper was deposited at the top surface as well. The vias were filled within 30 minutes when the top surface was completely blocked.