Xiao-Ming Fang

Wideband DHBTs using a graded carbon-doped InGaAs base

We report an InP/InGaAs/InP double heterojunction bipolar transistor (DHBT), fabricated using a mesa structure, exhibiting 282 GHz f/sub /spl tau// and 400 GHz f/sub max/. The DHBT employs a 30 nm InGaAs base with carbon doping graded from 8/spl middot/10/sup 19//cm/sup 3/ to 5/spl middot/10/sup 19//cm/sup 3/, an InP collector, and an InGaAs/InAlAs base-collector superlattice grade, with a total 217 nm collector depletion layer thickness. The low base sheet (580 /spl Omega/) and contact (<10 /spl Omega/-/spl mu/m/sup 2/) resistivities are in part responsible for the high f/sub max/ observed.

Sub-300 nm InGaAs/InP Type-I DHBTs with a 150 nm collector, 30 nm base demonstrating 755 GHz f max and 416 GHz f T

We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a simple mesa structure. The devices employ a 30 nm highly doped InGaAs base and a 150 nm InP collector containing an InGaAs/InAlAs superlattice grade. These devices exhibit a maximum f_max = 755 GHz with a 416 GHz /f_T. This is the highest f_max reported for a mesa HBT. Through the use of i-line lithography, the emitter junctions have been scaled from 500-600 nm down to 250-300 nm -all while maintaining similar collector to emitter area ratios. Because of the subsequent reduction to the base spreading resistance underneath the emitter R_b,spread and increased radial heat flow from the narrower junction, significant increases to f_max and reductions in device thermal resistance θ_JA are expected and observed. The HBT current gain β ≈ 24-35, BV_ceo = 4.60 V, BV_cbo = 5.34 V, and the devices operate up to 20 mW / μm² before self-heating is observed to affect the DC characteristics.

InGaAs/InP DHBTs with 120-nm collector having simultaneously high f/sub /spl tau//, f/sub max//spl ges/450 GHz

InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBT) have been designed for increased bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 450 GHz f/sub /spl tau// and 490 GHz f/sub max/, which is the highest simultaneous f/sub /spl tau// and f/sub max/ for any HBT. The devices have been scaled vertically for reduced electron collector transit time and aggressively scaled laterally to minimize the base-collector capacitance associated with thinner collectors. The dc current gain /spl beta/ is /spl ap/ 40 and V/sub BR,CEO/=3.9 V. The devices operate up to 25 mW//spl mu/m/sup 2/ dissipation (failing at J/sub e/=10 mA//spl mu/m/sup 2/, V/sub ce/=2.5 V, /spl Delta/T/sub failure/=301 K) and there is no evidence of current blocking up to J/sub e//spl ges/12 mA//spl mu/m/sup 2/ at V/sub ce/=2.0 V from the base-collector grade. The devices reported here employ a 30-nm highly doped InGaAs base, and a 120-nm collector containing an InGaAs/InAlAs superlattice grade at the base-collector junction.

Collector-pedestal InGaAs/InP DHBTs fabricated in a single-growth, triple-implant process

This letter reports InP/In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (DHBTs) employing an N/sup +/ subcollector and N/sup +/ collector pedestal-formed by blanket Fe and patterned Si ion implants, intended to reduce the extrinsic collector-base capacitance C/sub cb/ associated with the device footprint. The Fe implant is used to compensate Si within the upper 130 nm of the N/sup +/ subcollector that lies underneath the base ohmic contact, as well as compensate the /spl sim/1-7/spl times/10/sup -7/ C/cm/sup 2/ surface charge at the interface between the indium phosphide (InP) substrate and the N/sup

InP/InGaAs/InP double heterojunction bipolar transistors with 300 GHz F/sub max/

/collector drift layer. By implanting the subcollector, C/sub cb/ associated with the base interconnect pad is eliminated, and when combined with the Fe implant and selective Si pedestal implant, further reduces C/sub cb/ by creating a thick extrinsic collector region underneath the base contact. Unlike previous InP heterojunction bipolar transistor collector pedestal processes, multiple epitaxial growths are not required. The InP DHBTs here have simultaneous 352-GHz f/sub /spl tau// and 403-GHz f/sub max/. The dc current gain /spl beta//spl ap/38, BV/sub ceo/=6.0 V, BV/sub cbo/=5.4 V, and I/sub cbo/<50 pA at V/sub cb/=0.3 V.

60nm collector InGaAs/InP Type-I DHBTs demonstrating 660 GHz f T , BV CEO = 2.5V, and BV CBO = 2.7V

We report InP/InGaAs/InP Double Heterojunction Transistors (DHBTs) with high breakdown voltages in a substrate transfer process. A device with a 400 /spl Aring/ thick graded base, a 500 /spl Aring/ chirped superlattice base-collector grade and a 2500 /spl Aring/ thick InP collector exhibits f/sub /spl tau//=165 GHz and f/sub max/=300 GHz with breakdown voltage BV/sub CEO/=6 V at a current density, J/sub e/=1/spl middot/10/sup 5/ A/cm/sup 2/. A device with a 400 /spl Aring/ thick graded base, a 500 /spl Aring/ chirped superlattice base-collector grade and a 1500 /spl Aring/ thick InP collector exhibits f/sub /spl tau//=215 GHz and f/sub max/=210 GHz with breakdown voltage BV/sub CEO/=4 V at a current density, J/sub e/=1/spl middot/10/sup 5/ A/cm/sup 2/.

Strain relaxation and dislocation filtering in metamorphic HBT and HEMT structures grown on GaAs substrates by MBE

We report InP/InGaAs/InP double heterojunction bipolar transistors (DHBT) fabricated using a conventional mesa structure. The devices employ a 14 nm highly doped InGaAs base and a 60 nm InP collector containing an InGaAs/InAlAs superlattice grade. Devices employing a 400 nm emitter exhibit a maximum fT = 660 GHz with a 218 GHz f max - this is a record fT for a DHBT. The devices have been scaled vertically for reduced base and collector electron transit times, and the base-collector mesa has been further scaled to minimize the capacitance Ccb associated with the base contact area. The peak current gain beta ap 95, BVCEO = 2.5 V, BV CBO = 2.7 V, and the devices operate in excess of 30 mW/mum 2

MBE growth of large diameter InP-based lattice-matched and metamorphic HBTs

The production of InP-based epiwafers on GaAs substrates by molecular beam epitaxy is achieved through the use of metamorphic buffers (M-buffers) consisting of graded InAlAs or bulk InP layers. Each M-buffer demonstrates a unique surface morphology and strain relaxation mechanism, as demonstrated by AFM, SEM, and TEM. HEMTs and HBTs were grown on GaAs substrates using the two M-buffers, and their transport properties and dc parameters were compared with baseline structures grown on InP substrates. The structures grown with the InAlAs M-buffer were much closer to the baseline than those grown using the InP M-buffer. Incomplete dislocation filtering in the InP M-buffer may be the source of this degradation.

In/sub 0.53/Ga/sub 0.47/As/InP Type-I DHBTs w/ 100 nm collector and 491 GHz f,415 GHz f/sub max/

InAlAs/InGaAs/InP heterojunction bipolar transistor (HBT) structures were grown lattice-matched on InP substrates and metamorphically on GaAs substrates by molecular beam epitaxy. Generic structures with a thin base of 500 /spl Aring/ and doped at 4/spl times/10/sup 19/ cm/sup -3/ were chosen to support the frequency response required for advanced wireless and fiber-optic telecommunication products. Beryllium- and carbon-doped large-area devices were found to exhibit similar DC characteristics. No significant difference in current gain or linearity was observed for metamorphic devices compared to their lattice-matched counterparts.

250 nm InGaAs/InP DHBTs w/650 GHz /spl conint/ max and 420 GHz /spl conint/τ, operating above 30 mW/μm 2

In/sub 0.53/Ga/sub 0.47/As/InP double heterojunction bipolar transistors (Type-I DHBT) have been designed and fabricated having 100 nm drift collector and 30 nm highly doped base. The DHBTs have been scaled vertically for reduced electron transit time and aggressively scaled laterally to minimize the base-collector capacitance C/sub cb/ associated with thinner collectors. Devices employing a proven effective InGaAs/InAlAs superlattice base-collector grade (42 nm transition) exhibit a 491 GHz f and 415 GHz f/sub max/ and show no signs of current blocking until P>20 mW//spl mu/m/sup 2/ due to device self-heating. We also report devices of the same layer structure where the base-collector transition has been thinned to 25 nm exhibiting a 465 GHz f and 416 GHz f/sub max/ and show no signs of current blocking until J/sub e/>9 mA//spl mu/m/sup 2/ at 2.0 V/sub ce/ associated with the base-collector grade. For both, the DC current gain >40, V/sub BR,CEO/=3.1 V, and similar ideality factors n/sub c/, n/sub b/.