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Dive into the research topics where Xiaolong Ma is active.

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Featured researches published by Xiaolong Ma.


Nanoscale Research Letters | 2015

Novel 14-nm Scallop-Shaped FinFETs (S-FinFETs) on Bulk-Si Substrate

Weijia Xu; Huaxiang Yin; Xiaolong Ma; Peizhen Hong; Miao Xu; Lingkuan Meng

In this study, novel p-type scallop-shaped fin field-effect transistors (S-FinFETs) are fabricated using an all-last high-k/metal gate (HKMG) process on bulk-silicon (Si) substrates for the first time. In combination with the structure advantage of conventional Si nanowires, the proposed S-FinFETs provide better electrostatic integrity in the channels than normal bulk-Si FinFETs or tri-gate devices with rectangular or trapezoidal fins. It is due to formation of quasi-surrounding gate electrodes on scalloping fins by a special Si etch process. The entire integration flow of the S-FinFETs is fully compatible with the mainstream all-last HKMG FinFET process, except for a modified fin etch process. The drain-induced barrier lowering and subthreshold swing of the fabricated p-type S-FinFETs with a 14-nm physical gate length are 62 mV/V and 75 mV/dec, respectively, which are much better than those of normal FinFETs with a similar process. With an improved short-channel-effect immunity in the channels due to structure modification, the novel structure provides one of possibilities to extend the FinFET scalability to sub-10-nm nodes with little additional process cost.


Journal of Semiconductors | 2015

Device parameter optimization for sub-20 nm node HK/MG-last bulk FinFETs

Miao Xu; Huaxiang Yin; Huilong Zhu; Xiaolong Ma; Weijia Xu; Yongkui Zhang; Zhiguo Zhao; Jun Luo; Hong Yang; Chunlong Li; Lingkuan Meng; Peizheng Hong; Jinjuan Xiang; Jianfeng Gao; Qiang Xu; Wenjuan Xiong; Dahai Wang; Junfeng Li; Chao Zhao; Dapeng Chen; Simon Yang; Tianchun Ye

Sub-20 nm node bulk FinFET PMOS devices with an all-last high-k/metal gate (HK/MG) process are fabricated and the influence of a series of device parameters on the device scaling is investigated. The high and thin Fin structure with a tapered sidewall shows better performance than the normal Fin structure. The punch through stop layer (PTSL) and source drain extension (SDE) doping profiles are carefully optimized. The device without SDE annealing shows a larger drive current than that with SDE annealing due to better Si crystal regrowth in the amorphous Fin structure after source/drain implantation. The band-edged MG has a better short channel effect immunity, but the lower effective work function (EWF) MG shows a larger driveability. A tradeoff choice for different EWF MGs should be carefully designed for the devices scaling.


IEICE Electronics Express | 2015

Gate-All-Around Silicon Nanowire Transistors with channel-last process on bulk Si substrate

Xiaolong Ma; Huaxiang Yin; Peizhen Hong

For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conventional bulk-Si FinFET. It provides a stable way for the introduction of nanowire transistors in the FinFETs process for mass productions. The fabricated n-type transistors with the effective nanowire diameter (DNW) of 12 nm∼17 nm and the gate length of 100 nm demonstrated excellent subthreshold characteristics (subthreshold swing = 64mV/V and drain induced barrier lowering = 24mV/V). Meanwhile, it’s found that the H2 baking process as well as the optimized interface gate oxidation on NW channels greatly improved the device’s SS and off-current parameters.


Archive | 2015

Method of manufacturing stacked nanowire mos transistor

Huaxiang Yin; Changliang Qin; Zuozhen Fu; Xiaolong Ma; Dapeng Chen


Microelectronic Engineering | 2017

Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs

Changliang Qin; Huaxiang Yin; Guilei Wang; Peizhen Hong; Xiaolong Ma; Hushan Cui; Yihong Lu; Lingkuan Meng; Haizhou Yin; Huicai Zhong; Jiang Yan; Huilong Zhu; Qiuxia Xu; Junfeng Li; Chao Zhao; Henry H. Radamson


Archive | 2016

FINFET DEVICE AND METHOD FOR MANUFACTURING THE SAME

Huaxiang Yin; Xiaolong Ma; Weijia Xu; Qiuxia Xu; Huilong Zhu


ECS Solid State Letters | 2015

Self-Aligned Fin-On-Oxide (FOO) FinFETs for Improved SCE Immunity and Multi-VTH Operation on Si Substrate

Xiaolong Ma; Huaxiang Yin; Peizhen Hong; Weijia Xu


Solid-state Electronics | 2016

Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs

Changliang Qin; Guilei Wang; Peizhen Hong; Jinbiao Liu; Huaxiang Yin; Haizhou Yin; Xiaolong Ma; Hushan Cui; Yihong Lu; Lingkuan Meng; Jinjuan Xiang; Huicai Zhong; Huilong Zhu; Qiuxia Xu; Junfeng Li; Jian Yan; Chao Zhao; Henry H. Radamson


Archive | 2013

Method for manufacturing cascaded stacked nanowire mos transistor

Huaxiang Yin; 殷华湘; Xiaolong Ma; 马小龙; Weijia Xu; 徐唯佳; Qiuxia Xu; 徐秋霞; Huilong Zhu; 朱慧珑


Archive | 2015

Method for manufacturing semiconductor device including doping epitaxial source drain extension regions

Huaxiang Yin; Changliang Qin; Xiaolong Ma; Guilei Wang; Huilong Zhu

Collaboration


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Huaxiang Yin

Chinese Academy of Sciences

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Chao Zhao

Chinese Academy of Sciences

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Zuozhen Fu

Chinese Academy of Sciences

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Changliang Qin

Chinese Academy of Sciences

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Dapeng Chen

Chinese Academy of Sciences

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Peizhen Hong

Chinese Academy of Sciences

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Qiuxia Xu

Chinese Academy of Sciences

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Huilong Zhu

Chinese Academy of Sciences

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Jiang Yan

Chinese Academy of Sciences

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Lingkuan Meng

Chinese Academy of Sciences

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