Xiaoyong Li

A capacitor cross-coupled common-gate low-noise amplifier

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET f/sub T/, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated common-source LNA (CSLNA). A capacitor cross-coupled g/sub m/-boosting scheme is described that improves the NF and retains the advantages of the CGLNA topology. The technique also enables a significant reduction in current consumption. A fully integrated capacitor cross-coupled CGLNA implemented in 180-nm CMOS validates the g/sub m/-boosting technique. It achieves a measured NF of 3.0 dB at 6.0 GHz and consumes only 3.6 mA from 1.8 V; the measured input-referred third-order intercept ( IIP3) value is 11.4 dBm. The capacitor cross-coupled g/sub m/-boosted CGLNA is attractive for low-power fully integrated applications in fine-line CMOS technologies.

G/sub m/-boosted common-gate LNA and differential colpitts VCO/QVCO in 0.18-/spl mu/m CMOS

The demand for radio frequency (RF) integrated circuits with reduced power consumption is growing owing to the trend toward system-on-a-chip (SoC) implementations in deep-sub-micron CMOS technologies. The concomitant need for high performance imposes additional challenges for circuit designers. In this paper, a g/sub m/-boosted common-gate low-noise amplifier (CGLNA), differential Colpitts voltage-controlled oscillators (VCO), and a quadrature Colpitts voltage-controlled oscillator (QVCO) are presented as alternatives to the conventional common-source LNA and cross-coupled VCO/QVCO topologies. Specifically, a g/sub m/-boosted common-gate LNA loosens the link between noise factor (i.e., noise match) and input matching (i.e., power match ); consequently, both noise factor and bias current are simultaneously reduced. A transformer-coupled CGLNA is described. Suggested by the functional and topological similarities between amplifiers and oscillators, differential Colpitts VCO and QVCO circuits are presented that relax the start-up requirements and improve both close-in and far-out phase noise compared to conventional Colpitts configurations. Experimental results from a 0.18-/spl mu/m CMOS process validate the g/sub m/-boosting design principle.

Design considerations for CMOS low-noise amplifiers

A low-noise amplifier is the first active stage of a CMOS RF receiver. The inductively degenerated common-source LNA (CS-LNA) topology is currently popular because it achieves high gain, low noise figure, etc. The amplifiers performance is reviewed and the optimum Q value that gives the minimum noise figure is derived. It is then compared to the conventional common-gate LNA (CG-LNA) in terms of gain, noise figure, input matching, reverse isolation and stability. Finally, a general g/sub m/-boosted design technique for common-gate RF circuits is introduced that provides lower noise figure and power consumption than the conventional CS-LNA and CG-LNA stages; it also preserves the CG-LNA insensitivity to parasitic input capacitances. In view of CMOS scaling, the CG-LNA topology is attractive for future higher frequency and/or lower power designs.

A CMOS 3.1-10.6 GHz UWB LNA employing stagger-compensated series peaking

A fully-integrated common-gate UWB LNA employs a stagger-compensated series peaking technique to extend bandwidth, and a capacitor cross-coupled gm-boosting technique to reduce NF and power. A simple input matching scheme obviates the use of multiple inductors and complex filters. For two versions in 0.18 mum CMOS, BW extension factors are 4.1times and 4.9times, -3dB bandwidths are 1.3-10.7 GHz and 1.3-12.3 GHz, NF are 4.4 dB and 4.6 dB, peak S21 are 8.5 dB and 8.2 dB, and peak IIP3 are 8.3 dBm and 9.1 dBm, respectively. Each differential LNA draws 2.5 mA from 1.8 V

Compact model generation for on-chip transmission lines

An approach for the fast and accurate generation of compact distributed circuit models for on-chip transmission lines on lossy silicon substrates is presented. Using a novel ABCD matrix partitioning procedure, accurate distributed circuit models are extracted from scattering parameters obtained from measurements and calibrated full-wave electromagnetic simulations for a small set of transmission-line geometries spanning ranges of design parameter values. A feedforward artificial neural network is trained using the extracted results, and applied to generate accurate compact models for arbitrary values within the bounds of the training ranges. Consequently, the model generation time is greatly reduced compared to conventional approaches by exploiting the interpolation capabilities of the neural network. The compact model generator is fully compatible with HSPICE and SPECTRE-RF and is easily incorporated into parasitic-aware RF circuit design and optimization tools.

Low-power g/sub m/-boosted LNA and VCO circuits in 0.18 /spl mu/m CMOS

A 5.8GHz fully integrated common-gate LNA uses a g/sub m/-boosting technique and draws 1.9mA from a 1.8V supply with 9.4dB gain 7.6dBm IIP3, and 2.5dB NF. A Colpitts differential VCO (QVCO) employs a similar method and draws 3.6mA (4.3mA) from a 2V supply. Phase noise at 50kHz and 1 MHz offset frequencies are -97dBc/Hz (-104Bc/Hz) and -128 dBc/Hz (-127dBc/Hz), respectively.

A resonant pad for ESD protected narrowband CMOS RF applications

As CMOS applications move into the 5.6 GHz UNII band and approach the 10 GHz X-band, the opposing cost and performance design criteria collide. CMOS is extremely susceptible to damage from electro-static discharge (ESD) because CMOS devices are inherently capacitive. Unfortunately, the ESD structure typically used to protect CMOS integrated circuits contributes substantial parasitic capacitance to an RF signal path and is a major impediment to performance. The ESD protection circuitry adversely affects the performance of the low noise amplifier (LNA), often the most critical component in an RF CMOS receiver chain. This paper considers the novel approach of placing a second bond wire acting as an inductor in parallel with the parasitic capacitance of the ESD structure to effectively tune it out. All of the important parasitic effects are modeled and a procedure to incorporate them into the design of a resonating pad is described. Results from simulations using SpectreRF (a Cadence Design Systems simulation tool) show marked improvement in the LNA performance when using the resonating pad compared to conventional pad/ESD designs.

Circuit techniques for CMOS multiple-antenna transceivers

Circuit techniques are described for multiple-antenna transceivers. A device desensitization technique aimed at simultaneously realizing the optimum noise and input match in LNA circuits is followed by a transformer-coupling technique in common-gate LNA circuits that reduces NF and power. Next, a Colpitts VCO improves start-up and maintains excellent phase-noise performance. Finally, a Cartesian combining method applied to MIMO transceivers is overviewed.

Accurate compact model extraction for on-chip coplanar waveguides

Employing a novel ABCD matrix partitioning technique, the proposed method extracts an accurate frequency-dependent distributed circuit model for the broadband characteristics of coplanar waveguide transmission lines using either measured or simulated scattering parameters. A neural network with a training algorithm is then applied to predict CPW performance for a range of geometry sizes. The circuit model validated using EM (MOMENTUM) and circuit (HSPICE) simulations demonstrates good accuracy, high computational efficiency, and fast model development.