Y.Hiruta

An 820 pin PGA for ultra large-scale BiCMOS devices

A high-pin-count, high-performance pin grid array (PGA) has been developed for future ASIC devices using half-micron BiCMOS technology and having a maximum usable gate count of 300k. The package has been designed with due consideration of all package functions, electrical, thermal, and mechanical. A surface mount type pin joint was adopted to realize high wiring density on the printed wiring board. The package has 820 pins with a 50-mil pitch and five rows. A highly accurate tape automated bonding (TAB) technology was applied to the die assembly to achieve narrow pitch and high pad count for the bonding between the die and the package. The thermal resistance from the die to the ambient is lower than 1.5 degrees C/W at 1 m/s air flow velocity. The electrical parameters of the package were quantified. The high reliability of the package and surface mount type soldering has been confirmed. >

Electrical characterization of packaging environment using switching noise generating vehicle

A CMOS test vehicle which generates simultaneous switching noise programmably is described. It is effective to evaluate noise level under a practical packaging environment, such as single-chip packages or multichip modules in any power/ground structures. Measured data can be used to verify the effective inductance of the package electrical model.<<ETX>>

Design optimization of wiring substrate in a CMOS-based multichip module

The effects of line resistance on the electrical performance in CMOS-based MCMs are described. Switching noise, ringing noise, interconnect delay, and crosstalk noise in the line resistance range of a thin-film wiring substrate are discussed. Signal line resistance works as a damping resistor both for switching noise and for signal ringing noise. There are optimum damping conditions. The chip-to-chip delay was not substantially influenced by the line resistance as long as the line length was kept short. The line resistance, i.e. the characteristic impedance, as well as the line resistance has an important role in determining the signal propagation properties whether it behaves like an RC delay or it is in the region of the time of flight. The design of the wiring substrate must be optimized for CMOS buffer drivability to have good electrical properties and not to impose excessive requirements on thin-film process technology.<<ETX>>