Kazuhide Doi

Flip chip underfill reliability of CSP during IR reflow soldering

Reliability of flip chip CSP (Chip Scale Package) was investigated. The underfill resin for CSP has high saturation content of moisture absorption, compared to a conventional mold resin. The IR reflow test showed no delamination at the underfill interfaces and no package cracking in a flip chip CSP with a ceramic substrate and voidless underfill under the JEDEC LEVEL 1 and 2 conditions. However, it was found out that delamination and package cracking occurred in the IR reflow test under the JEDEC LEVEL 1 when the flip chip CSP has voids in the underfill. The underfill reliability results by IR reflow test confirmed superior reliability of the flip chip CSP with a ceramic substrate and void controlled underfill.

Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA

Eutectic solder flip chip fabrication technology, through bumping to assembly process, has been developed. In bumping process, electroplating method and thick photo resist process could form eutectic solder bumps whose uniformity of height are less than 10% within wafer. Eutectic solder flip chip assembly process, which includes bonding, cleaning and underfilling, has been also developed. Bonding process of eutectic solder indicates good self-alignment. The excellent rosin cleaning was achieved by the ultrasonic cleaning process with Techno Care. In underfilling process, the underfill resin which can be applied to small stand-off have been chosen. Reliability tests for CSP and flip chip interconnection were carried out and confirmed the good reliability of fabrication process using eutectic solder flip chip technology.

Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps

This paper describes effective thin‐film structure barrier metals for use as eutectic solder bumps. Shear strength and bump interconnection resistance were evaluated. The mutual diffusion in metals was investigated. Barrier metal structures —Cu/Ti,Ni/Ti and Cu/Cr—were evaluated after ageing. The Ni/Ti structure has good reliability according to ageing test results. Pd is used for improvement of solder wettability and as an oxidisation barrier. Consequently, it was concluded that a thin‐film Pd/Ni/ Ti barrier metal is suitable for use as eutectic solder bumps. The broken interfaces of the solder bumps were analysed by scanning auger electron spectrometry. In the thin‐film Cu/Ti structure, decrease in the shear strength is caused by three mechanisms, as determined from the broken interface analysis. The three mechanisms are mixed metal formation, Ti oxidisation and diffusion between barrier metals and Al. Furthermore, TCT and PCT were carried out on these eutectic solder bumps to confirm the interconnection...

Flux free flip chip attach technology for BGA/CSP packages

The solder flip chip attach without flux using plasma treatment has been developed in order to eliminate the flux residue cleaning process for manufacturing the BGA/CSP packages. The plasma treatment is composed of roughening the solder surface and improving the solder wettability. Argon gas added hydrogen (Ar+H/sub 2/) plasma has been very superior to argon plasma for etching/roughening the solder surface, therefore, a mixed gas plasma composed of carbon tetrafluoride and argon or oxygen(CF/sub 4//Ar or CF/sub 4//O/sub 2/) has modified the solder surface for good solderability without damage to the Si chip, the passivation film and the organic substrate because of the active solder surface. After the Si chip was mounted on the organic substrate with the solder bumps treated with plasma, the solder bumps were renewed at 230/spl deg/C and underfilled. Package reliability has been demonstrated by the temperature cycle test (TCT) and temperature humidity bias test (THB) and this flux free flip chip attach technology with plasma treatment has been sufficiently verified such that it can be applied to packaging processes.