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Featured researches published by Hiroshi Tazawa.


Microelectronics Reliability | 2003

Polymer film deposition with fine pitch openings by stencil printing

Hirokazu Ezawa; Masaharu Seto; Masahiro Miyata; Hiroshi Tazawa

Abstract It is confirmed that stencil printing with a novel developed printable polyimide paste can be used for polymer film deposition on LSI wafers. A thick polyimide film with openings for solder ball bumping can be deposited on all of the LSIs on a wafer by stencil printing at one time. This stencil printing process does not need an expensive lithography process, providing cost-effective wafer-level chip scale packages (WLCSPs). In this study, a novel polyimide paste was tailored to have a higher thixotropy ratio than conventional printable polyimide materials. The novel printable polyimide paste shows that the viscosity ratio of more than 3.5 at the shear rate of 1 to 10 s−1 and that the viscosity increases rapidly after the shear rate is lowered. Fine spaces of 40 μm between 250 μm openings were obtained for 10 μm thick polyimide films on Si wafers. It has been also confirmed that the new paste shows the variation range of 30 μm at the opening size of 385 μm within 100 continuously printed wafers. Even after the new paste was shear-thinned repeatedly, rheological behavior of the new paste was not changed. This robustness leads to higher efficiency of the materials for mass-producing. From the reliability viewpoint of the printed polyimide films, no peelings were observed on plasma-CVD SiN films after the pressure cooker test under the condition of 127 °C and 0.25 MPa with the humidity of 100% for 300 h. The optimal stencil printing process using the novel developed paste will lead to significant cost reduction of a patterned polymer deposition process. Finally, WLCSPs using the stencil printing of the new polyimide paste have been demonstrated for SRAM LSIs on 8-in. wafers.


electronic components and technology conference | 1995

A new bonding mechanism of 50 /spl mu/m pitch TAB-ILB with 0.25 /spl mu/m Sn plated Cu lead

Eiichi Hosomi; Chiaki Takubo; Hiroshi Tazawa; Koji Shibasaki; Yoichi Hiruta; Toshio Sudo

A 50 /spl mu/m pitch TAB has been developed by applying newly developed TAB tape and inner lead bonding technology. A new electrodeposited Cu foil which has a high tensile strength and 18 /spl mu/m thickness was adopted as the lead material. Sn plating on the inner leads has been thinned to 0.25 /spl mu/m from the conventional 0.6 /spl mu/m to avoid excess alloy formation. The inner leads were gang-bonded to the Au bumps. The cross sections of the bonded region were observed by SEM and EPMA for the specimens before and after high temperature storage (HTS), The Au-Sn fillets formed by the bonding supported the inner leads at the initial state. Ternary Au-Cu-Sn alloy was also formed at the interface between the inner lead and the bump. After HTS, cracks formed between the fillet and the inner lead, and the fillets could not contribute to supporting the inner lead. The ternary Au-Cu-Sn alloy which was formed at the bottom of the inner lead in ILB processes transformed to binary Cu-Au alloys after HTS. Sn was driven away from the lead-bump interface. The binary Cu-Au alloys kept the bonding strength after HTS. A destructive lead pull test was performed before and after HTS. The failure mode was a lead fracture in all cases.


Archive | 1992

Semiconductor assembly having laminated semiconductor devices

Hiroshi Tazawa; Chiaki Takubo; Yoshiharu Tsuboi; Mamoru Sasaki


Archive | 1996

Flip chip mounting type semiconductor device

Naohiko Hirano; Kazuhide Doi; Chiaki Takubo; Hiroshi Tazawa; Eiichi Hosomi; Yoichi Hiruta; Takashi Okada; Koji Shibasaki


Archive | 1996

Semiconductor device comprising fine bump electrode having small side etch portion and stable characteristics

Eiichi Hosomi; Chiaki Takubo; Hiroshi Tazawa; Ryouichi Miyamoto; Takashi Arai; Koji Shibasaki


Archive | 1997

Flip-chip connection type semiconductor integrated circuit device

Takashi Okada; Naohiko Hirano; Hiroshi Tazawa; Eiichi Hosomi; Chiaki Takubo; Kazuhide Doi; Yoichi Hiruta; Koji Shibasaki


Archive | 1996

Semiconductor device, method of fabricating the same and copper leads

Eiichi Hosomi; Hiroshi Tazawa; Chiaki Takubo; Koji Shibasaki


Archive | 1996

Tape carrier and assembly structure thereof

Eiichi Hosomi; Chiaki Takubo; Hiroshi Tazawa; Koji Shibasaki


Archive | 1992

Semiconductor device using film carrier

Chiaki Takubo; Hiroshi Tazawa; Yoshiharu Tsuboi; Masao Mochizuki


Archive | 1995

Semiconductor device having a bump electrode connected to an inner lead

Eiichi Hosomi; Chiaki Takubo; Hiroshi Tazawa; Koji Shibasaki

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