H. J. Joo

Highly reliable and mass-productive FRAM embedded smartcard using advanced integration technologies

We developed FRAM embedded smartcard in which FRAM replace EEPROM and SRAM to improve the read/write cycle time and endurance of data memories in smartcard. Highly reliable sensing window for FRAM embedded smartcard was achieved by advanced integration technologies such as novel capacitor technology, multi-level encapsulating barrier layer (EBL) technology, and optimal inter-metallic dielectrics (IMD) technology.

A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

Advanced Integration Process Technology for Highly Reliable Ferroelectric Devices

The retention properties were improved by optimizing capacitor process and developing advanced integration process. The retention trends of ferroelectric capacitors before integration were systematically investigated as a function of critical process parameters such as baking temperature and annealing temperature and time. It was found that the ferroelectric capacitors show best retention properties by double annealing process with high baking temperature of 330°C. The optimized ferroelectric capacitors were integrated into 32 Mb FRAM with 0.44 μm2 cell size and 0.25 μm design rule, and evaluated for their retention behavior. Since the retention properties of real cell size capacitors were closely correlated with sensing window, it was focused on enhancing the sensing window by high etching slope and chemical mechanical planarization (CMP) process. It was demonstrated that the retention properties were greatly improved by using optimal capacitor process and advanced integration process.

Novel integration technologies for highly manufacturable 32 Mb FRAM

Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.

Highly manufacturable and reliable 32 Mb FRAM technology with novel BC and capacitor cleaning process

In this paper, the 32Mb FRAM were fabricated by enhancing the sensing window using several novel integration technologies such as highly oriented PZT films, seam-free BC technology and special capacitor cleaning technology.

Electrical properties of highly reliable 32 Mb FRAM with advanced capacitor technology

Highly reliable 32Mb FRAM was successfully developed by double annealing technique and CVD deposition technique. The optimized annealing method generates highly (111) oriented ferroelectric films, resulting in large remnant polarization. The CVD process provides strong interface between electrode and ferroelectric films, giving rise to minimal integration degradation and strong retention properties. After baking test at 150 /spl deg/C for 100hrs, a wide sensing window of 350 mV was achieved to guarantee strong retention properties for high density FRAM products.

Improvement in Reliability of 0.25 μ m 15F2 FRAM Using Novel MOCVD PZT Technology

We report on the measurements of reliability of 0.25 μ m 15F2 cell FRAM using novel MOCVD PZT technology. The MOCVD PZT capacitors were prepared using a pre-purging process and successfully integrated into the 32 Mb FRAM process with double EBL technology and optimal ILD/IMD scheme. After full integration, the 0.44 μ m2 MOCVD PZT capacitors with a 2Pr value of 35 μ C/cm2 at an applied voltage of 2.7 V show superior retention properties. The MOCVD PZT cells have large sensing windows of 420 mV at an operation voltage of 2.7 V. The sensing windows show only a slight decrease during 100 hours of baking at a temperature of 150°C, after which not a single cells is observed to fail. Therefore, it is clearly demonstrated that using the novel MOCVD PZT capacitors, high reliability of 0.25 μ m 15 F2 cell FRAM can be achieved.

Novel Common Cell Via and Etch Stopper Technology for 0.25 μM 1T1C 32 MBIT FRAM

In the 0.25 μm FRAM technology generation, it is extremely difficult to define the hole-type cell via on very small top electrode area, because there is no process margin for the hole type cell via. Therefore, a runner via technology based on line-type cell via with Ir etch stopper is developed for 0.25 μm FRAM technology generation. However, it was found that the severe charge degradation occurred during the runner cell via process. It was found that the stress of Ir film plays a dominant role in degrading the capacitor value. Since the Ir film shows severe severe stress variation from compressive to tensile during heating and cooling, the ferroelectric capacitors using the Ir etch stopper show the charge degradation during integration. Therefore, we developed a common cell via scheme and stable PE-SiN etch stopper which possess compressive stress and high etching selectivity against PSG film for replacing Ir etch stopper. The polarization value of ferrolectric capacitor was not degraded after etch-stopper process. The 0.25 μm ferroelectric capacitors exhibited excellent P r value of 15 μC/cm2 after completing whole process integration, which guarantees a reliable high yield.

Integration and Electrical Properties of Novel Ferroelectric Capacitors for 0.25 µm 1 Transistor 1 Capacitor Ferroelectric Random Access Memory (1T1C FRAM)

Since the space margin between capacitors has been greatly reduced in 32 Mb high-density ferroelectric random access memory (FRAM) with a 0.25 µm design rule, considering the limitation of current etching technology, the stack height of ferroelectric capacitors should be minimized for stable node separation. In this paper, novel capacitors with a total thickness of 4000 A were prepared using a seeding layer, low temperature processing, and optimal top electrode annealing. The 1000 A Pb(Zr1-xTix)O3 (PZT) films showed excellent structural and ferroelectric properties such as strong (111) orientation and large remanent polarization of 40 µC/cm2. The low stack capacitors were then implemented into 0.6 µm and prototype 0.25 µm FRAM. Compared to a conventional capacitor stack, the ferroelectric capacitors exhibited adequate sensing margin of 250 fC, thus giving rise to a fully working die of 4 Mb FRAM. Therefore, it was clearly demonstrated that the novel capacitors can enable the realization of a high-density 32 Mb FRAM device with a 0.25 µm design rule.

Quality assured mass productive 1.6V operational 0.18 /spl mu/m 1T1C FRAM embedded smart card with advanced integration technologies against defectives

We have made great progress for mass production of a highly reliable 1.6V, 0.18 mum 1T1C FRAM embedded smart card. For mass production, our device has to pass standard qualification tests on the package level. These contain the infant life test (ILT), the high temperature operating life (HTOL), the endurance and the high temperature storage (HTS) test. Problems in the PZT capacitor integration scheme led to single bit fails during the standard ILT, HTOL and HTS tests. The causes are broken EBL and TE/PZT interface damage, which were removed by the modification of top electrode deposition and capacitor etching processes and by a new capping oxide deposition scheme