Y. Nakagome

An experimental 1.5-V 64-Mb DRAM

Low-voltage circuit technologies for higher-density dynamic RAMs (DRAMs) and their application to an experimental 64-Mb DRAM with a 1.5-V internal operating voltage are presented. A complementary current sensing scheme is proposed to reduce data transmission delay. A speed improvement of 20 ns was achieved when utilizing a 1.5-V power supply. An accurate and speed-enhanced half-V/sub CC/ voltage generator with a current-mirror amplifier and tri-state buffer is proposed. With it, a response time reduction of about 1.5 decades was realized. A word-line driver with a charge-pump circuit was developed to achieve a high boost ratio. A ratio of about 1.8 was obtained from a power supply voltage as low as 1.0 V. A 1.28 mu m/sup 2/ crown-shaped stacked-capacitor (CROWN) cell was also made to ensure a sufficient storage charge and to minimize data-line interference noise. An experimental 1.5 V 64 Mb DRAM was designed and fabricated with these technologies and 0.3 mu m electron-beam lithography. A typical access time of 70 ns was obtained, and a further reduction of 50 ns is expected based on simulation results. Thus, a high-speed performance, comparable to that of 16-Mb DRAMs, can be achieved with a typical power dissipation of 44 mW, one tenth that of 16-Mb DRAMs. This indicates that a low-voltage battery operation is a promising target for future DRAMs. >

Sub-1-V swing internal bus architecture for future low-power ULSIs

A bus architecture is proposed for reducing the operating power of future ULSIs. It uses new types of bus driver circuits and bus receiver circuits to reduce the bus signal swing while maintaining a low standby current. The bus driver circuit has a source offset configuration, achieved by the use of low-V/sub T/ MOSFETs and an internal supply voltage corresponding to the reduced signal swing. The bus receiver circuit has a symmetric configuration with two-level conversion circuits, each of which consists of a transmission gate and a cross-coupled latch circuit. Fast level conversion is achieved without increasing the standby current. The combination of the new bus driver and receiver enables the bus swing to be reduced to one-third that of the conventional architecture while maintaining high-speed data transmission and a low standby current. A test circuit designed and fabricated using 0.3- mu m processes verifies the operation of the proposed architecture. Further improvements in the speed performance are possible with device optimization. >

An experimental large-capacity semiconductor file memory using 16-levels/cell storage

In recent years, high density and high speed file memories have become increasingly important for achieving higher performance in computer systems. Multilevel storage dynamic memories offer advantages in terms of speed and density for file usage. An experimental 4Mbit memory has been designed and fabricated utilizing a newly developed multilevel storage scheme and unique peripheral circuits. These include a staircase pulse generator for multilevel storage operation, a voltage regulator for maintaining storage level accuracy, an error correcting circuit for protecting the data from alpha-particle-induced soft error, and a timing generator for testing the device as a fully integrated LSI memory.

Limitations and challenges of multigigabit DRAM chip design

This paper describes the limitations and challenges involved in designing gigabit DRAM chips in terms of high-density devices, high-performance circuits, and low-power/low-voltage circuits. The key results obtained are as follows. 1) For formation of a MOSFET shallow junction, which suppresses threshold voltage (V/sub T/) variation and offset voltage of sense amplifiers, reduction in ion-implantation energy and process temperature is essential. Also, the keys in terms of area, speed, stable cell operation, and ease of fabrication are use of low-resistivity multilevel metal wiring and high permittivity materials and three-dimensional memory cells to reduce a difference in height between the memory cell array and the surrounding peripheral circuits. 2) For creation of a high speed, the keys are memory-subsystem technology such as pipeline operation, wide-bit I/O, low-voltage interfaces, and high-density packaging. Embedded DRAM further enhances the speed and throughput by using massively parallel processing of signals on a large number of data-lines and reducing internal bus capacitances. 3) For power reduction, the key continues to be reduction of the data-line dissipating charge through both partial activation of multidivided data-lines and lowering of the data-line voltage. Ultralow-voltage operation, essential to drastic power reduction, can be achieved by subthreshold-current reduction circuits such as source-gate backbiasing, multi-V/sub T/, dynamic V/sub T/, and node-boosting schemes.

The impact of data-line interference noise on DRAM scaling

A kind of data-line (DL) interference noise in a scaled DRAM cell array is found and studied through analysis. The dynamic behavior of cell arrays due to sense-amplifier operation is derived analytically. Analysis shows that the amount of interference noise is more than three times larger than expected from simple data-line coupling. A novel experimental technique for precise noise determination is developed to verify the analysis. Analytical results are in good agreement with the experimental data. It is found that the interference noise plays a dominant role in determining the operating margin of the DRAM and that a novel process or a cell array architecture for minimizing the interference noise is indispensable in 16-Mb DRAM and beyond. >

Sub-1-/spl mu/A dynamic reference voltage generator for battery-operated DRAMs

A new reference voltage generator with ultralow standby current of less than 1 /spl mu/A is proposed. The features are: 1) a merged scheme of threshold voltage difference generator and voltage-up converter with current mirror circuits, and 2) intermittent activation technique using self-refresh clock for the DRAM. This combination enables the average current to be reduced to 1/100 and the resistance of trimming resistor to be reduced to 1/10 compared to conventional reference voltage generators, while maintaining high accuracy and high stability. The proposed circuit was experimentally evaluated with a test device fabricated using 0.3-/spl mu/m process. An initial error of less than 4% for 6 trimming steps of the trimming resistor, temperature dependence of less than 370 ppm//spl deg/C from room temperature to 100/spl deg/C, and output noise of less than 12 mV for 1 V/sub p/spl minus/p/ V/sub cc/ bumping are achieved. These results are sufficient for achieving high-density battery operated DRAMs with low active and data-retention currents comparable to SRAMs. >

A new stacked cell structure for giga-bit DRAMs using vertical ultra-thin SOI (DELTA) MOSFETs

Summary form only given. The first stacked DRAM (dynamic RAM) cell using vertical ultra-thin SOI (silicon-on-insulator) MOSFET (DELTA, or fully depleted lean-channel transistor) is proposed. Since the ultra-thin SOI structure provides high noise immunity, the storage node capacitance can be reduced by more than 50%. Therefore, in the proposed DRAM cell a large storage capacitor need not be essential, and this will extend the DRAMs miniaturization to the gigabit levels. The cell structure schematic is shown and threshold voltage dependences on channel length of DELTA-, conventional NMOS-, and PMOS-FETs are demonstrated. DELTA shows good short channel characteristics compared to conventional NMOS.<<ETX>>

A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure

Low-noise, high-speed circuit techniques for high-density DRAMs (dynamic random-access memories), as well as their application to a single 5-V 16-Mb CMOS DRAM with a 3.3-V internal operating voltage for a memory array, are described. It was found that data-line interference noise becomes unacceptably high (more than 25% of the signal) and causes a serious problem in 16-Mb DRAM memory arrays. A transposed data-line structure is proposed to eliminate the noise. Noise suppression below 5% is confirmed using this transposed data-line structure. A current sense amplifier is also proposed to maintain the data-transmission speed in common I/O lines, in spite of a reduced operating voltage and increased parasitic capacitance loading in the memory array. A speed improvement of 10 ns is achieved. Using these circuit techniques, a 16-Mb CMOS DRAM with a typical RAS access time of 60 ns was realized. >

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAM

A dual-operating-voltage scheme (5 V for peripheral circuits and 3.3 V for the memory array) is shown to be the best approach for a single 5-V 16-Mb DRAM (dynamic random-access memory). This is because the conventional scaling rule cannot apply to DRAM design due to the inherent DRAM word-line boosting feature. A novel internal voltage generator to realize this approach is presented. Its features are the switching of two reference voltages, a driver using a PMOS-load differential amplifier, and the word-line boost based on the regulated voltage, which can ensure a wider memory margin than conventional circuits. This approach is applied to an experimental 16-Mb DRAM. A 0.5% supply-voltage dependency and 30-ns recovery time are achieved. >

A 16-levels/cell dynamic memory

A multilevel storage dynamic memory using a standard DRAM memory cell array is presented. A staircase word pulse and a charge-transfer preamplifier are used for converting binary data to multilevel storage voltages and vice versa. The 16-level (4-bit)/cell READ/WRITE operation has been confirmed at storage levels as low as 80-100 mV. The storage-level voltage accuracy is limited basically by subthreshold leakage current.