Y. S. Chen

Low power and high speed bipolar switching with a thin reactive Ti buffer layer in robust HfO2 based RRAM

A novel HfO2-based resistive memory with the TiN electrodes is proposed and fully integrated with 0.18 mum CMOS technology. By using a thin Ti layer as the reactive buffer layer into the anodic side of capacitor-like memory cell, excellent memory performances, such as low operation current (down to 25 muA), high on/off resistance ratio (above 1,000), fast switching speed (5 ns), satisfactory switching endurance (>106 cycles), and reliable data retention (10 years extrapolation at 200degC) have been demonstrated in our memory device. Moreover, the benefits of high yield, robust memory performance at high temperature (200degC), excellent scalability, and multi-level operation promise its application in the next generation nonvolatile memory.

Evidence and solution of over-RESET problem for HfO X based resistive memory with sub-ns switching speed and high endurance

The memory performances of the HfOX based bipolar resistive memory, including switching speed and memory reliability, are greatly improved in this work. Record high switching speed down to 300 ps is achieved. The cycling test shed a clear light on the wearing behavior of resistance states, and the correlation between over-RESET phenomenon and the worn low resistance state in the devices is discussed. The modified bottom electrode is proposed for the memory device to maintain the memory window and to endure resistive switching up to 1010 cycles.

Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti Cap

The memory performance of hafnium oxide (HfOx)-based resistive memory containing a thin reactive Ti buffer layer can be greatly improved. Due to the excellent ability of Ti to absorb oxygen atoms from the HfOx film after post-metal annealing, a large amount of oxygen vacancies are left in the HfOx layer of the TiN/Ti/HfOx/TiN stacked layer. These oxygen vacancies are crucial to make a memory device with a stable bipolar resistive switching behavior. Aside from the benefits of low operation power and large on/off ratio (>100), this memory also exhibits reliable switching endurance (>106 cycles), robust resistance states (200°C), high device yield (~100%), and fast switching speed (<10 ns).

High Gamma Value 3D-Stackable HK/MG-Stacked Tri-Gate Nanowire Poly-Si FETs With Embedded Source/Drain and Back Gate Using Low Thermal Budget Green Nanosecond Laser Crystallization Technology

Three-dimensional sequentially stackable high-k/metal-gate-stacked tri-gate nanowire poly-Si FETs with embedded source/drain (e-S/D) and back gate were demonstrated. The highly crystallized channel, fabricated by green nanosecond laser crystallization, chemical mechanical polish, and post-surface modification processes, enhances the electrical property of the tri-gate nanowire FET. The e-S/D structure reduces the contact and series resistances caused by the nanowire structure. Thus, the fabricated n/p-type tri-gate nanowire poly-Si FETs exhibit steep subthreshold swings (96/125 mV/decade), high ON-currents (232/110 μA/μm), and ION/IOFF ratio (>105). Furthermore, the independent back gate with thin back gate oxide can easily adjust the threshold voltage of the tri-gate nanowire transistor and results in high gamma value (>0.05) FET realizing sequentially stacked and low Vdd (0.6 V) operable inverter.

Enabling low power BEOL compatible monolithic 3D+ nanoelectronics for IoTs using local and selective far-infrared ray laser anneal technology

Local and selective far-infrared ray laser annealing (FIR-LA) process with very short heating duration (<;100μs) and low substrate temperature (<;400°C) enables sequentially stacked gate-first nanowire FETs (NWFETs), including 3D⁺ Si NWFET and poly-Ge junctionless (JL) NWFET, and BEOL compatible monolithic 3D⁺ nanoelectronics. The 3D⁺ Si NWFETs, demonstrated by green nano-second laser crystallization (GNS-LC) and FIR-LA processes exhibit steep subthreshold swing (<;90mV/dec.) and high driving current (n-type: 310μA/μm and p-type: 220μA/μm). The 7nm poly-Ge JLNWFET shows high I_on/I_off ratio (>5×10⁴) and small DIBL. Furthermore, the thus fabricated low driving voltage 6T SRAM shows a static noise margin (SNM) of 130 mV at Vd=0.4V enabling the low power and low cost 3D⁺IC for internet of things (IoTs).

Scalability issue in Ti/HfO bipolar resistive memory with 1T-1R configuration by resistance pinning effect during 1 st RESET and its solution

The scalability issue of 1T-1R Ti/HfOx BRM, which is resulted from the interaction between BRM and transistor, is demonstrated. While a sufficiently lower Vforming can mitigate the RP, an alternative buffer layer Ta is also proposed to further scale the 1T-1R HfOx based BRM.

Overview and Future Challenges of Hafnium Oxide ReRAM

Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, Y. Y. Hsu, W. H. Liu, C. H. Tsai, S. M. Wang, S. S. Sheu, P. C. Chiang, W. P. Lin, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Institute of Electronics Engineering, National Tsing Hua University, Department of Chemical and Materials Engineering, MingShin University of Science & Technology, Taiwan R.O.C., Phone: 886-3-5912958, Fax: 886-3-5917690, E-mail: yusheng@itri.org.tw

Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D + IC

A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D+IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (Tsub<;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at VDD=0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.

Improvement of switching uniformity and scalability in 1T-1R HfO x -based bipolar resistive memory with Zr inserting layer

1T-1R Zr/HfO_x RRAM with improved uniformity is proposed, which is due to the easily O_xidation of Zr layer from both HfO_x and supporting SiO₂. The formation of ZrO_x become a good current limiter which help the device prevent scalability issue.

Ultra-high LRS Nonlinearity and high speed in HfOX Based Complementary Resistive Switch with Ti electrode for Vertical RRAM

with Ti electrode for Vertical RRAM Yu-Sheng Chen, Pang-Shiu Chen, Heng-Yuan Lee, Kan-Hsueh Tsai, Tai-Yuan Wu, Fred Chen, and Ming-Jinn Tsai Electronics and Optoelectronics Research Laboratory, Industrial Technology Research Institute, Hsinchu 310, Taiwan. Department of Chemical and Materials Engineering, MingShin University of Science & Technology Hsinfong, Hsinchu 304, Taiwan, Phone : 886-3-5593142 ext 3377, Fax : 886-3-5593142, E-mail :pschen@must.edu.tw Abstract A reactive Ti of 5 nm thick can improve the memory window of HfOx device with complementary resistive switch (CRS). The CRS HfOx device exhibits high LRS nonlinearity (>1000), robust retention at 150 °C, and enough endurance (>1000) at 40 ns speed. A plausible mechanism is proposed.