Yang Xiu

Soft-Failures Induced by System-Level ESD

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground.

Analysis of Active-Clamp Response to Power-On ESD: Power Supply Integrity and Performance Tradeoffs

An active rail clamp circuit provides protection against component-level ESD; this work explores the challenges associated with designing a rail clamp to additionally provide protection when the IC is powered on. The fast transient response required to protect against ESD makes it difficult to design a stable circuit and introduces tradeoffs between supply integrity and the clamping characteristic. This work presents an analysis of how these performance metrics are affected by device sizes. Interactions between a rail clamp circuit, which may be an active or passive clamp, and the parasitic elements of the package and board are examined; it is shown that these interactions may briefly power down the supply.

S-parameter based modeling of system-level ESD test bed

The IEC 61000-4-2 test bed is modeled with circuit elements extracted from S-parameter measurements. Simulated current waveforms are consistent with measurement for both battery operated and tethered equipment-under-test without customizing the model parameters for each case.

Practical methodology for the extraction of SEED models

A custom test board facilitates TLP characterization of the external pins of an integrated circuit. Models extracted from the data are used to simulate the pin-level response of the IC to an IEC 61000-4-2 discharge. ESD gun zaps are applied to the test board; simulated and measured waveforms are compared.

On-Chip monitors of supply noise generated by system-level ESD

Two supply noise monitor circuits are demonstrated on a 130-nm test chip. These monitors are capable of providing quantitative measurements of on-chip supply voltage perturbations resulting from system-level ESD. Circuit-level simulations reproduce all trends found in the measurement results.

Chip-Level ESD-induced noise on internally and externally regulated power supplies

Power integrity during system-level ESD is studied on two test chips that have different integrated voltage regulator designs. On-chip voltage regulation can provide increased immunity to ESD-induced noise, especially if the internally-generated power supply does not utilize any off-chip decoupling capacitors.

Experimental study of supply voltage stability during ESD

On-chip power supply integrity may be compromised during a power-on ESD event, e.g. system-level ESD. Experimental data are provided to show that the supply integrity is a function of the rail clamp gain, its speed of response to ESD, and the amount of on-chip supply decoupling capacitance. It is also demonstrated that just a few nH of package inductance can cause the on-chip supply to briefly collapse, regardless of the rail clamp response speed.

Case study of DPI robustness of a MOS-SCR structure for automotive applications

This paper presents a case study to demonstrate that transient-triggered ESD protection circuits may fail the DPI automotive requirement. A novel scheme is devised to improve the DPI performance of a MOSSCR protection device while maintaining the system-level ESD performance.

Current challenges in component-level and system-level ESD simulation

Electronic systems and components contain large numbers of elements and have a complex non-linear response to ESD; thus, passing ESD qualification on the first pass is unlikely to occur unless the robustness is verified by means of simulation prior to manufacturing. For component-level ESD verification, the primary challenge is in regards to computational efficiency; for system-level ESD verification, component and test bed modeling present major challenges.

Improving the long pulse width failure current of NPN in BiCMOS technology

The pulse width dependency of the failure current for NPN structures in a 0.18-μm BiCMOS technology is studied using measurements and TCAD simulation. The desired “Wunsch-Bell” behavior is not observed due to formation of current filaments in this device; however, the failure current for long pulse widths can be increased by layout changes.