Hiroki Shinkawata

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

A 312MHz 16Mb random-cycle embedded DRAM macro with 73/spl mu/W power-down mode for mobile applications

An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.

Analysis of Soft Failures in Low-Resistance Interconnect Vias Using Doubly Nesting Arrays

An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting array structure. Applying this technique to the development of a 40-nm CMOS technology, a soft failure with about ten times larger than normal via resistance could be efficiently detected and located.

Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doubly nesting array

We report newly developed Test-Element-Group for detecting soft failures of low-resistance-element like interconnect via using doubly nesting array. We detected the soft failure of fine via which resistance had about 10 times larger resistance than normal via using this structure manufactured in 40nm CMOS technology.

A memory cell capacitor with Ba/sub x/Sr/sub 1-x/TiO/sub 3/ (BST) film for advanced DRAMs

The stored charges in the capacitor of the DRAM cell are decreased, as the power supply voltage and the memory cell area are reduced on the trend of the dimension shrinkage. To get sufficient capacitance of memory cell is one of the most important requirements for the advanced DRAMs. Therefore, a high-dielectric constant material has been proposed for memory cells of DRAM. It has been indicated that BST films realize the equivalent SiO2 thickness of 0.47 nm for the capacitor dielectric film of 256M DRAM. In this study, the process technology of the simple planar stacked cell with the BST film is developed. The memory cell capacitor with the high-dielectric constant BST film is applied to the fully functional 4M DRAM, in order to investigate the compatibility with the full DRAM fabrication process. The fabrication technology for the memory cell of DRAM with BST film capacitors and the DRAM performance are described.<<ETX>>

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time with forward BB is 1.84 ns at 1.0 V overdrive and 25°C, which is improved by 60% and thus we achieved over 380 MHz operation. Up to 20% active read power reduction is also achieved by using proposed localized adoptive wordline width control.

SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive

Ultra low power performance is indispensable for Micro Controller Unit (MCU) used as wireless sensor and communication nodes which needs battery maintenance free and energy harvesting operation in the Internet of things (IoT) era. The Silicon on Thin Buried Oxide (SOTB) is one of the most suitable CMOS technology for ultra low power MCU because of its small variability and back bias controllability. This paper describes the mechanism of ultra low power performance of SOTB, performance demonstration of transistor, SRAM and MCU test chip, and what SOTB will realize for IoT and Automotive. SOTB will have less than 1/10 of power efficiency by low leakage current at standby mode and low current consumption at operation mode which todays technology cannot realize.

Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via

We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S). Abnormally high resistance as a soft failure via was detected and located in a 40nm CMOS technology. We captured a soft failure bit which had a high resistance via exhibiting over 160 times larger one.