Yen-Hsiang Wang

A 144GHz 0.76cm-resolution sub-carrier SAR phase radar for 3D imaging in 65nm CMOS

Millimeter-Wave-based radar has gained attention in recent years for automotive and object detection applications. Several new applications are also emerging which employ mm-Wave radar techniques to construct short range mm-Wave 3D imaging systems for security screening and biomedical applications. At present, these types of 3D mm-Wave imagers have only been demonstrated in lll-V technology, as CMOS-based radar suffers several range and resolution limitations due to limited output power and linearity.Most CMOS mm-Wave radar systems used in automotive applications are based on Frequency-Modulated Continuous-Wave (FMCW) ranging techniques in which the carrier is swept to produce a frequency offset at the receiver output proportional to the round-trip distance between the radar and target. While FMCW is an excellent approach for accurate ranging, its implementation becomes particularly difficult at high frequencies as the resolution is heavily dependent on sweep linearity and the high RF front-end performance required to support the wideband swept carrier. For 3D mm-Wave imaging applications, this high operating frequency is indispensable as the attainable spatial (XY) resolution is fundamentally limited by the wavelength of the imaging system. Higher frequency also helps relax focusing lens requirements, as the optical diffraction limit is set by the ratio of the radar wavelength over the lens aperture size.

A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate gain mismatches within channels. Moreover, the channel offset mismatches are calibrated through the digital- controlled corrective current sources embedded in the track-and-hold amplifiers of each sub-ADC. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consuming 40 mW at 2.2 GS/s from a 1 V supply. Measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate. The effective number of bits (ENOB) is 6.0 bits at Nyquist rate, and the figure-of-merit (F.O.M.) is 0.28 pJ/conv.-step. This prototype has also been integrated into a gigabit self-healing wireless transceiver SoC.

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with −111dBc/Hz in-band phase noise and an FOM of −242dB

The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs a new time-to-digital conversion technique based on sub-sampling phase detection. It is accomplished by directly sampling the analog voltage signal at the PLLs high frequency node and converting it into a digital code. This achieves a higher time resolution with less power.

A low-overhead self-healing embedded system for ensuring high yield and long-term sustainability of 60GHz 4Gb/s radio-on-a-chip

The available ISM band from 57-65GHz has become attractive for high-speed wireless applications including mass data transfer, streaming high-definition video and even biomedical applications. While silicon based data transceivers at mm-wave frequencies have become increasingly mature in recent years [1,2,3], the primary focus of the circuit community remains on the design of mm-wave front-ends to achieve higher data rates through higher-order modulation and beamforming techniques. However, the sustainability of such mm-wave systems when integrated in a SoC has not been addressed in the context of die performance yield and device aging. This problem is especially challenging for the implementation of mm-wave SoCs in deep sub-micron technology due to its process & operating temperature variations and limited ft / fmax with respect to the operation frequency.

A

A D-band CMOS transmitter is presented with an integrated injection-locked frequency-tripling synthesizer, digital control, and an on-chip antenna. It employs an IF feed-forward pre-distortion scheme, which improves gain compression of the transmitter to provide an overall higher linearity gain profile, allowing reduced power back-off for higher peak-to-average modulation schemes. The integrated D-band transmitter consumes 347 mW and occupies 1800× 1500 μm of silicon area. The proposed transmitter delivers 0.4 dBm of effective isotropic radiated power with a saturated power on-chip of at least 12.2 dBm. The transmitter has a peak power-added efficiency (PAE) of 4.8% with power delivered to the antenna and a peak PAE of 0.31% when considering radiated power.

D

This paper presents a new power combining scheme, which has either one or four amplifiers on depending upon the levels of input signal. This approach realized by utilizing a unique combiner that is lossless and has constant gain under both scenarios. As a result, for the system where variable output power is required, this combining scheme can be used in an amplifier design with optimum efficiency. Measurement data show 15% power efficiency for the four-amplifier scenario and 28% for the single amplifier scenario at 13dBm input power. We also investigate the possibility of using this combiner in an envelope tracking amplifier.

-Band CMOS Transmitter With IF-Envelope Feed-Forward Pre-Distortion and Injection-Locked Frequency-Tripling Synthesizer

We have realized a 200GHz 4×4 focal plane array (FPA) by using super-regenerative receiver (SRR) pixels made of 65nm CMOS for mm-wave imaging applications. With 16 pixel elements constructed on PCB, the FPA consumes 215mA under 1V power supply. Such realization is made possible by carefully analyzing the super-regenerative interference (SRI) commonly observed in close-spaced SRRs and applying a newly developed quench synchronization scheme to suppress the undesired SRI.

A new amplifier power combining scheme with optimum efficiency under variable outputs

A 7-bit, 2.2-GS/s time-interleaved subranging CMOS ADC for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. A novel time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. In addition, a low-power and fast-settling distributed resistor array for reference voltages is proposed to mitigate mismatches within channels. The prototype is implemented in 65 nm CMOS, occupying only 0.3 mm2 chip area and consumes 40 mW at 2.2 GS/s from a 1 V supply. Measured SNDR and SFDR are 38 dB and 46 dB, respectively, with a 1.08 GHz input at 2.2 GS/s sampling rate.

A 200 GHz 16-pixel focal plane array imager using CMOS super regenerative receivers with quench synchronization

A CMOS D-band 135-150 GHz transmitter is presented with integrated digital control and on-chip antenna. The proposed transmitter employs an IF feed-forward compensation scheme which improves the soft gain compression of the power amplifier by 5.1dB to provide an overall more linear AM-AM profile allowing reduced power back-off for modulation schemes with a high peak-to-average ratio. The proposed D-band transmitter consumes 255mW and occupies 2000 × 1500 um of silicon area. The proposed transmitter delivers a 0.4 dBm EIRP and a saturated power on chip of 13.2 dBm. The transmitter has a peak PAE of 8.2% with power delivered to the antenna and a peak PAE of 0.4% when considering radiated power.

A 40-mW 7-bit 2.2-GS/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS

With the coming era of Big Data, hardware implementation of machine learning has become attractive for many applications, such as real-time object recognition and face recognition. The implementation of machine learning algorithms needs intensive memory access, and SRAM is critical for the overall performance. This paper proposes a new design of high speed SRAM for machine learning purposes. With fast access time (cycle time: 650 ps, access time: 350 ps), low sensitivity to temperature variation and high configurability (less than 10% performance difference between 125_rcw_tt vs 0_rcw_tt), the proposed SRAM is a better candidate for hardware machine learning system than the conventional SRAM. Compared with Samsung HL 152, our design has smaller size (121×43 um2 vs 127×44 um2) with half the number of pins ports (12 vs 25) and higher speed (2.2GHz vs 0.8GHz).