Yoon Jong Song

Integration and electrical properties of diffusion barrier for high density ferroelectric memory

A reliable Ir diffusion barrier was prepared on polysilicon plugged substrate with a contact size of 0.6 μm. Using a Ti adhesion layer and stress-relief process, it was possible to integrate the Ir barrier into a high density 4 Mb ferroelectric random access memory device. After heat treating sol-gel derived Pb(Zr1−xTix)O3 (PZT) films at 700 °C, the Ir barrier contact displayed an ohmic behavior and showed a low resistance of 130 Ω per contact in 1k serial contact array. The PZT films on Pt/IrO2/Ir poly-plugged substrate exhibited excellent ferroelectric properties such as remnant polarization and coercive voltage of 25 μC/cm2 and 1.15 V, respectively. Auger depth profile and transmission electron microscopy analyses confirmed that no appreciable oxidation was formed between the Ir barrier and the polysilicon plug.

Electrical properties of highly reliable plug buffer layer for high-density ferroelectric memory

A CoSi2 buffer layer was prepared in polycrystalline silicon (polysilicon) plug for preventing an undesired microvoid between the polysilicon plug and Ir/Ti diffusion barrier. Since the microvoid generates random function fail, resulting in low wafer yield of a 4 Mb ferroelectric random access memory device, we developed the thermally stable CoSi2 buffer layer for eliminating the random single bit fails. The ferroelectric capacitors using the CoSi2 buffer layer showed a low contact resistance of 96 Ω per contact in 1k serial contact array with contact size of 0.6 μm, and also exhibited great ferroelectric properties such as remnant polarization and coercive voltage of 20 μC/cm2 and 1.2 V, respectively. Scanning electron microscopy analyses confirmed that no microvoid was formed between the interface between the Ir/Ti barrier layer and the CoSi2 buffer layer.

Improvement in the electrical properties in Pt/Pb(Zr0.52Ti0.48)O3/Pt ferroelectric capacitors using a wet cleaning method

A wet cleaning solution was designed to specifically eliminate nonferroelectric phases, such as pyrochlore, PbO, and the etching damaged layer. Scanning electron microscopy pictures clearly showed that treatment with the cleaning solution completely removed these nonferroelectric phases. After removing the nonferroelectric phases, ferroelectric properties such as remnant polarization, coercive voltage, and leakage current, were remarkably improved. In addition, the wet cleaned ferroelectric capacitors yielded superior endurance against hydrogen-induced damage compared to those of the noncleaned capacitors.

Deposition-temperature-dependent stress of capping oxide and its effect on Pt/Pb(Zr1−xTix)O3/Pt ferroelectric capacitor

Two different interlayer dielectric (ILD) materials, electron cyclotron resonance chemical vapor deposition oxide (ECR-OXIDE) and plasma enhanced chemical vapor deposition TEOS oxide (PE-TEOS), were prepared at 400 and 200 °C respectively, on silicon substrates and Pt/Pb(Zr1−xTix)O3 (PZT)/Pt capacitors. It was found that the ILD deposition temperature is a most important parameter for minimizing the degradation of remnant polarization (Pr) during the ILD deposition. Since the stress of PZT capacitor strongly depends on the ILD deposition temperature, the PZT capacitor with PE-TEOS showed more compressive stress than that with ECR-OXIDE, which results in severe Pr degradation of PZT capacitor with PE-TEOS. This large stress effect of PE-TEOS was confirmed by x-ray diffraction (XRD) patterns in which the d spacing of (111) PZT films with PE-TEOS was much larger than that of PZT films with ECR-OXIDE. Therefore, the low ILD deposition temperature is a key parameter for achieving an ILD integration without any...

What Lies Ahead for Resistance-Based Memory Technologies?

Phase-change RAM, magnetic RAM, and resistive RAM offer strong scalability, speed, and power consumption advantages over conventional capacitance-based memory. Recent work shows the feasibility of mass producing these new devices and their suitability for next-generation technology.

Ring Contact Electrode Process for High Density Phase Change Random Access Memory

It is very important to maintain stable cell uniformity for reliable operation and wide sensing margin since the writing current is mainly governed by the bottom electrode contact (BEC) size which is especially sensitive to small process variation. In order to accomplish low writing current with uniform cell distribution, advanced storage module technology using ring type BEC was proposed. Using this, it was possible to achieve flat and uniform BEC, which results in a wide sensing margin and high manufacturability. Finally, we firstly fabricated advanced ring type contact structure and firstly evaluated based on high density 256 Mbytes phase change random access memory (PRAM) with small cell size technologies.

Current and Future High Density FRAM Technology

Current high density FRAM devices have been fabricated by developing several novel integration technologies such as capacitor technology and process technology. The process technology minimizes the integration degradation using stable BC scheme, encapsulating barrier layer (EBL), and effective etching curing process. The capacitor technology generates robust ferroelectric capacitors to be immune to any integration damage by taking advantage of new ferroelectric films and CVD deposition technique. Future FRAM technology will be focused on etchless scheme, nano-scale ferroelectric films, and three-dimensional capacitor scheme using CVD deposition techniques for noble metal electrode with excellent step coverage, which will produces high density 256 Mb FRAM and beyond.

A novel diffusion barrier using oxygen stopping layer for high density FRAM

Abstract A novel diffusion barrier was successfully developed by using an oxygen stopping layer between Ir barrier films. The oxygen stopping layer was generated by inserting a Ti layer between Ir films, which results in the sandwiched form of Ir/Ti/Ir multi-layer. The diffusion barrier properties were enhanced by refraining oxygen from penetrating into polysilicon plug, which might be attributed to the reaction of oxygen with the Ir-Ti layer. It was confirmed in Auger depth profile that the oxygen was well localized in the stopping layer after annealing at 700°C for 10 min in O2 ambient. The multi-stack barrier exhibited low contact resistance of 320 and 650 ohm for contact size of 0.6×0.6 and 0.4×0.4 μm2, respectively. The PZT films prepared on Pt/IrO2/Ir-Ti-Ir/poly substrate shows remnant polarization of 20 μC/cm2 and coercive voltage of 1.2V at 5V. It was demonstrated that this novel barrier can solve barrier contact problem occurred in high density 16Mb FRAM.

Retention characteristics of Pb(Zr, Ti)O3 films deposited by various methods for high-density non-volatile memory

Retention loss is a significant issue for an application of ferroelectric thin films to high-density non-volatile memory devices. We investigated the polarization retention characteristics of ferroelectric Pb(Zr,Ti)O 3 (PZT) thin films which were fabricated on Pt/IrO 2 /Ir substrates by different deposition methods. In thermally-accelerated retention failure tests, Pb(Zr,Ti)O 3 (PZT) films which were prepared by a chmeical solution deposition (CSD) method showed rapid decay of retained polarization charges as the films became thinner down to 1000 A, while the films which were grown by metal organic chemical vapor deposition (MOCVD) showed relatively large nonvolatile charges at the same thickness. We concluded that in the CSD-grown films, the relatively large interfacial passive layer compared with the MOCVD-grown films had an unfavorable effect on retention behavior. We observed the existence of such interfacial layers by extrapolation of the total capacitance with thickness of the films and the capacitance of this layer was larger in MOCVD-grown films. It means that the possibility of the accumulation of space charges at the interface was reduced, so that less imprint and less retention loss could be observed in the MOCVD-grown films.

Highly reliable etching mask technology for high density fram

Abstract It is well known that ferroelectric capacitors are degraded during etching process due to its highly energetic ion bombardment. The etching damage is considered as the major cause of degrading the ferroelectric properties. In order to achieve high yield of 4Mb FRAM, the etching damage should be minimized. Therefore, it is strongly desired to develop a new etching mask technology for reducing the severe etching damage. In this paper, we investigated several etching mask technologies to choose proper mask for etching the noble metal layers. It was found that TiO2/PSG/TiN and PSG/TiN masks are very effective in minimizing the etching damage and enhancing the etching ability. The Pr value of etch-damaged cell was greatly improved from 5 μC/cm2 to 25 μC/cm2 by using the novel etching masks, resulting in high yield of 4Mb FRAM. As observed in TEM pictures, the ferroelectric capacitors prepared by TiO2/PSG/TiN and PSG/TiN masks are completely protected by the new mask technology.