Yi-Feng Chang

A 60 V Tolerance Transceiver With ESD Protection for FlexRay-Based Communication Systems

In this paper, a 60 V tolerance transceiver with ESD (electrostatic discharge) protection is proposed for FlexRay-based communication systems. The FlexRay transceiver comprises three protective devices, including an over-voltage detector, high-voltage ESD devices, and high-voltage diodes. The over-voltage detector is in charge of detecting bus (BP and BM) status to distinguish whether any hazard has happened. If the over-voltage detector is activated, the FlexRay transceiver must be turned off for safety. The high-voltage ESD device uses a base-floating PNP serving as a bi-directional device. Besides, it can protect the FlexRay transceiver whenever it is short-circuited in positive or negative high voltages. Notably, the high-voltage diode will eliminate the negative leakage current when negative high voltage hazards appear in FlexRay channels. An experimental prototype is implemented using a 0.18 μm CMOS mixed-signal based generation II HV BCD process. The measurement results justify the functional correctness and 60 V tolerance of the proposed FlexRay transceiver design.

FinFET SCR structure optimization for high-speed serial links ESD protection

An optimized SCR structure was proposed for high turn-on speed and low parasitic capacitance in FinFET CMOS process. Experimental results indicate that the proposed SCR structure delivers the best known results among the literatures (140mA/fF). By adopting the structure, ESD protection design for multi Gb/s transceiver can be simply realized.

Novel dual direction PNP with self-bias ring structure

A novel voltage rating adjustable dual direction PNP ESD clamp with self-bias ring structure is proposed and demonstrated for better isolation performance in this work. In comparison to conventional structure, measurements exhibit that the latch-up (LU) immunity are enhanced by more than 2.5X, and the leakage current level is simultaneously suppressed by more than 20X.

Bias Temperature Stress (BTS) induced ESD device's leakage issue and Its preventing solutions in smart power technology

A leakage issue induced by Bias Temperature Stress (BTS) is found in a NPN-based ESD clamp. BTS (1.1*Vdd, 125C, 8hrs) can cause an accumulation of drifted ions at an/the STI interface which leads to increased leakage and eventual device failure. TCAD simulation and activation energy extraction model are used to explain the mechanism and two solutions are proposed.

Novel SCR structure for power supply protection in FinFET technology

A FinFET SCR embedded ESD clamp for power supply protection with low leakage current is demonstrated. The proposed clamp is suitable for low power applications since it reduces ∼87% of leakage current per bigFET width and improves ESD robustness to ∼2X per footprint compared to the conventional RC-triggered clamp.