Yi-Hsuan Hsiao

A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

A double-layer TFT NAND-type flash memory is demonstrated, ushering into the era of three-dimensional (3D) flash memory. A TFT device using bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005, Lai et al., 2006) with fully-depleted (FD) poly silicon (60 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.2/0.09 mum) with excellent performance and reliability properties are achieved. The bottom layer shows no sign of reliability degradation compared to the top layer, indicating the potential for further multi-layer stacking. The present work illustrates the feasibility of 3D flash memory

A highly pitch scalable 3D vertical gate (VG) NAND flash decoded by a novel self-aligned independently controlled double gate (IDG) string select transistor (SSL)

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >;16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the worlds first <; 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

A critical examination of 3D stackable NAND Flash memory architectures by simulation study of the scaling capability

Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (∼20 nm) and poly channel thickness (∼10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F∼2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, “Z-interference” in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.

A Highly Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory

For the first time, a successful TFT NAND-type flash memory is demonstrated using a low thermal budget process suitable for stacking the memories. A TFT-SONOS device using bandgap engineered SONOS (BE-SONOS) (Lue, et al. 2005) with fully-depleted (FD) poly silicon (50 nm) channel and tri-gate P+-poly gate is integrated into a NAND array. Small devices (L/W=0.18/0.09 mum) with good DC performance are achieved, owing to the good control capability of the tri-gate FD structure. Successful NAND array functions are demonstrated, with more than 1 muA read current for a 16-string NAND array and good program disturb immunity. This new device also shows good endurance and data retention, and negligible read disturb. These results are very encouraging for future 3D flash memory

Reliability Model of Bandgap Engineered SONOS (BE-SONOS)

Reliability properties of bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) are extensively studied. First, the erase mechanism of BE-SONOS is confirmed as substrate hole tunneling through the ultra-thin ONO tunneling dielectric. Next, very long-term (>3,000 hours) high-temperature baking data (from 150 to 250degC) for various programmed/erased states and cycling history are collected and analyzed for a thorough understanding of the retention property. By transforming retention data (VFB-time) into de-trapping current (J) and modeling its dependence on electric field and temperature, the long-term retention of various programmed states are consistently and accurately predicted. This modeling technique avoids the ambiguity of the common Arrhenius plot, and is useful for developing other predictive models too. We have shown that BE-SONOS surpasses the 10-year 85degC storage criterion for Flash memory applications

Radically extending the cycling endurance of Flash memory (to > 100M Cycles) by using built-in thermal annealing to self-heal the stress-induced damage

Flash memory endurance is limited by the tunnel oxide degradation after repeated P/E stressing in strong electric field. Thermal annealing should be able to repair the oxide damage but such theory cannot be tested in real time since completed device cannot endure high temperature > 400°C and long baking time is impractical for real time operation. In this work, we propose and demonstrate a novel self-healing Flash, where a locally high temperature (>800°C), short time (ms) annealing is generated by a built-in heater. By modifying the word line (WL) from a single-ended to a double-ended structure, the WL can carry a current to generate Joule heating; and the proximity of the gate can readily heat the tunnel oxide of the Flash device, annealing out the damage caused by P/E cycling. We discover that a BE-SONOS charge-trapping NAND Flash device can be quickly annealed within a few milliseconds. With this novel technique, we demonstrate a record-high endurance of >100M (108) P/E cycles with excellent post-100M-cycle retention. Interestingly, the WL heater can be used to achieve faster erasing although normally FN tunneling should be temperature-independent. At the extreme temperature achieved in our heating-while-erasing experiments electron de-trapping from the charge trapping nitride, accompanying hole FN tunneling, also occurs, resulting in faster erasing. Finally, a novel design architecture for implementing the self-healing Flash memory is proposed.

A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BLs (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

A novel junction-free BE-SONOS NAND flash

We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.

Understanding STI edge fringing field effect on the scaling of charge-trapping (CT) NAND Flash and modeling of incremental step pulse programming (ISPP)

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures (including near-planar, body-tied FinFET, self-aligned (SA) STI, and gate-all-around (GAA) devices) is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Careful well doping optimization is necessary to suppress the parasitic leakage path and avoid the abnormal subthreshold current behavior. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). The complexity of the edge fringing field cannot be modeled by simple 1D tunneling, and by using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field especially after electrons are programmed into the channel. Moreover, because of edge fringing field effect more charge injection is required to obtain the same memory window when the device is scaled. We propose an analytical ISPP model. A field enhancement factor (FE) is introduced, and the FE gradually decreases with electron injection while Vt gets higher. Through this model the ISPP programming of various STI structures can be well understood. Finally, we find that the self-boosting program disturb window is proportional to the ISPP slope.