Yong-jin Yoon

A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM

A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.

Programmable and automatically adjustable on-die terminator for DDR3-SRAM interface

A new programmable and automatically adjustable off-chip driver (OCD) and on-die terminator (ODT) for DDR3-SRAM interface are proposed, to widen the valid data widow. The proposed OCD fills the role of the ODT, and the OCD and the ODT play a role in the ESD protection circuit. This application of 72 Mb DDR3-SRAM provides a 1.5 GHz data rate, and the valid data window of the DDR input signal is 540 ps. The proposed programmable impedance controller (PIC) maintains constant resistance of the ODT within a 3% variation, and supports DDR3-SRAM mode. A new scheme of updating impedance control codes to maintain uniform impedance and a stable power-up sequence for the ODT are also suggested.

Synchronous mirror delay for multiphase locking

A clock generation circuit having the function of multiphase locking was designed using the synchronous mirror delay (SMD) scheme. The internal clock can be synchronized to the external clock with intended phase difference. The synchronizing error of the clock generation circuit is reduced below the delay time of unit delay stage by compensation characteristics of detecting circuit in SMD. A 32-M double data rate (DDR) SRAM including the clock generation circuit is fabricated using 0.13-/spl mu/m CMOS technology. To measure the synchronizing error of the clock generation circuit, the test elements group (TEG) system is designed and fabricated with the main system. The synchronizing error of the clock generation circuit is far smaller than the delay time of unit delay stage at zero phase locking and similar to the delay time of unit delay stage at multiphase locking.

New dynamic logic-level converters for high performance application

Two new logic-level converting circuits are presented for high performance application. One of them is the dynamic logic-level converter (DLC). It has fast transition time in converting the logic-level, and its power consumption is smaller than that of conventional approaches. The other is a dynamic logic-level converter for duty ratio conserving (DDLC). The duty ratio or cycle of a level converted signal generated by the DDLC is equal to that of an input signal. The devices are applied to a 72 Mb DDR SRAM. The DLC and the DDLC allow the core of the chip to operate at a lower voltage level (1.2 V) than the I/O supply voltage level (1.5 V or 1.8 V). In this application, transition time of the DLC is less than 120 psec, and the duty cycle for signal converted by the DDLC are higher than that of an input signal by 1.1%. The area overhead in the chip is 0.03%.