Yong-Won Cha

Reduction of plasma-induced damage during intermetal dielectric deposition in high-density plasma

We have attempted to reduce the plasma-induced damage to the thin gate oxides during intermetal dielectric (IMD) gap-fill process by high-density plasma (HDP) chemical vapor deposition (CVD). It was revealed that the optimization of preheating step could reduce the damage. The H/sub 2/-based HDP CVD process was also effective in reducing plasma-induced damage compared with the conventional He-based process. The gate oxide failure was reduced remarkably at the low deposition temperatures less than 400/spl deg/C. Both the significant damage reduction and the excellent gap-fill performance were achieved by the adoption of the phosphorus silicate glass (PSG) using the low temperature H/sub 2/-based HDP CVD technique.

Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

A novel NF/sub 3/-HDP-CVD process for STI-filling in sub-90 nm DRAM and beyond

A complete filling of the shallow trench isolations (STI) in sub-90 nm DRAM is realized with the novel NF/sub 3/-HDP-CVD process. The gap-fill capability of the NF/sub 3/-HDP-CVD increased dramatically as NF/sub 3/ gas is added to the conventional SiH/sub 4//O/sub 2/ chemistry of HDP-CVD process. The effect of the NF/sub 3/-HDP-CVD processed STI is investigated by analyzing the transistor characteristics and yield in 512 M DRAM.