N. W. Jang

A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

Electrical properties of highly reliable plug buffer layer for high-density ferroelectric memory

A CoSi2 buffer layer was prepared in polycrystalline silicon (polysilicon) plug for preventing an undesired microvoid between the polysilicon plug and Ir/Ti diffusion barrier. Since the microvoid generates random function fail, resulting in low wafer yield of a 4 Mb ferroelectric random access memory device, we developed the thermally stable CoSi2 buffer layer for eliminating the random single bit fails. The ferroelectric capacitors using the CoSi2 buffer layer showed a low contact resistance of 96 Ω per contact in 1k serial contact array with contact size of 0.6 μm, and also exhibited great ferroelectric properties such as remnant polarization and coercive voltage of 20 μC/cm2 and 1.2 V, respectively. Scanning electron microscopy analyses confirmed that no microvoid was formed between the interface between the Ir/Ti barrier layer and the CoSi2 buffer layer.

Advanced Integration Process Technology for Highly Reliable Ferroelectric Devices

The retention properties were improved by optimizing capacitor process and developing advanced integration process. The retention trends of ferroelectric capacitors before integration were systematically investigated as a function of critical process parameters such as baking temperature and annealing temperature and time. It was found that the ferroelectric capacitors show best retention properties by double annealing process with high baking temperature of 330°C. The optimized ferroelectric capacitors were integrated into 32 Mb FRAM with 0.44 μm2 cell size and 0.25 μm design rule, and evaluated for their retention behavior. Since the retention properties of real cell size capacitors were closely correlated with sensing window, it was focused on enhancing the sensing window by high etching slope and chemical mechanical planarization (CMP) process. It was demonstrated that the retention properties were greatly improved by using optimal capacitor process and advanced integration process.

Novel integration technologies for highly manufacturable 32 Mb FRAM

Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.

A novel 1T1C capacitor structure for high density FRAM

In this paper, an etching damage-free 4 Mb ferroelectric random access memory (FRAM) integration technology was for the first time developed using ferroelectric (FE) hole capacitor structure. Since the PZT capacitors are not etched, no etching damage was generated in the novel capacitor structure. The etching process issue, which is one of most critical obstacles for scaling down FRAM device, is completely resolved by using this novel FE hole structure. Therefore, the novel integration technology strongly promises to provide a reliable scaling down of FRAM device beyond 0.25 /spl mu/m technology generation.

Highly manufacturable and reliable 32 Mb FRAM technology with novel BC and capacitor cleaning process

In this paper, the 32Mb FRAM were fabricated by enhancing the sensing window using several novel integration technologies such as highly oriented PZT films, seam-free BC technology and special capacitor cleaning technology.

Highly reliable etching mask technology for high density fram

Abstract It is well known that ferroelectric capacitors are degraded during etching process due to its highly energetic ion bombardment. The etching damage is considered as the major cause of degrading the ferroelectric properties. In order to achieve high yield of 4Mb FRAM, the etching damage should be minimized. Therefore, it is strongly desired to develop a new etching mask technology for reducing the severe etching damage. In this paper, we investigated several etching mask technologies to choose proper mask for etching the noble metal layers. It was found that TiO2/PSG/TiN and PSG/TiN masks are very effective in minimizing the etching damage and enhancing the etching ability. The Pr value of etch-damaged cell was greatly improved from 5 μC/cm2 to 25 μC/cm2 by using the novel etching masks, resulting in high yield of 4Mb FRAM. As observed in TEM pictures, the ferroelectric capacitors prepared by TiO2/PSG/TiN and PSG/TiN masks are completely protected by the new mask technology.

Novel Common Cell Via and Etch Stopper Technology for 0.25 μM 1T1C 32 MBIT FRAM

In the 0.25 μm FRAM technology generation, it is extremely difficult to define the hole-type cell via on very small top electrode area, because there is no process margin for the hole type cell via. Therefore, a runner via technology based on line-type cell via with Ir etch stopper is developed for 0.25 μm FRAM technology generation. However, it was found that the severe charge degradation occurred during the runner cell via process. It was found that the stress of Ir film plays a dominant role in degrading the capacitor value. Since the Ir film shows severe severe stress variation from compressive to tensile during heating and cooling, the ferroelectric capacitors using the Ir etch stopper show the charge degradation during integration. Therefore, we developed a common cell via scheme and stable PE-SiN etch stopper which possess compressive stress and high etching selectivity against PSG film for replacing Ir etch stopper. The polarization value of ferrolectric capacitor was not degraded after etch-stopper process. The 0.25 μm ferroelectric capacitors exhibited excellent P r value of 15 μC/cm2 after completing whole process integration, which guarantees a reliable high yield.

Highly scalable sub-10F/sup 2/ 1T1C COB cell for high density FRAM

Recently, technology innovation for high density and high performance FRAM has been pronounced. Among the breakthrough technologies for high density and high performance FRAM, 1T1C capacitor-on-bitline (COB) cell technology is essential because it can greatly reduce FRAM cell size compared to previous and current 2T2C FRAMs (Kinam Kim, 1999; Lee et al., 1999). Design improvement for enhanced sensing ability is also a promising technology for highly reliable mega-bit density FRAM (Jeon et al, 2000). Although the recent demonstration shows a promising future for stand-alone FRAM applications, current 1T1C COB FRAM still has incomparably large cell size factor compared to DRAM and flash. This is one of the most challenging issues that FRAM faces for developing high-density stand-alone memory. In this work, a novel cell structure for sub-10 F/sup 2/ cell size is for the first time developed. The key technologies for the sub-10 F/sup 2/ novel cell are: (1) advanced oxidation barrier and PZT film technologies which enables MIM ferroelectric capacitors to be lowered to /spl sim/500 nm thick stack: (2) single-mask capacitor etching technology which can produce >80/spl deg/ ferroelectric capacitor fence slope; (3) no cell via contact technology by which capacitor pitch can ideally be reduced to 2F; (4) an Al-reflow process which enables sub-0.4 /spl mu/m back-end interconnection without degrading the ferroelectric capacitor. The novel cell is demonstrated with an experimental 4 Mb FRAM, where the 1T1C COB cell is fabricated with folded bit line architecture and plate line-up sensing scheme.

Novel Damage Curing Technology on One-Mask Etched Ferroelectric Capacitor for Beyond 0.25 μm FRAM

In order to manufacture high-density ferroelectric random access memory (FRAM) device, it is required to develop one mask capacitor etching technology, because it can provide greatly reduced cell size. However, as the capacitor size shrinks further, the influence of etching damage on the ferroelectric properties becomes much serious due to the high ratio of perimeter/area for patterned capacitor. Since undesired polymeric etch byproducts were formed on sidewall of the edge cell capacitors in 32 Mb FRAM with 0.25 μm design rule, we developed novel post-etch curing technology using O2 plasma treatment with wet cleaning process. After the post-etch curing treatment, the hysteresis loops of block edge cells were almost identical to those of block center cells, which results in improving the relative 2Pr value as ratio of edge cells/center cells from 33% to 98%. In conclusion, novel curing technology was successfully developed for one mask etching damaged ferroelectric capacitor using O2 plasma treatment with wet cleaning process, resulting in high wafer yield.