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Dive into the research topics where Yoshihisa Sugiura is active.

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Featured researches published by Yoshihisa Sugiura.


international solid-state circuits conference | 1999

A 130-mm/sup 2/, 256-Mbit NAND flash with shallow trench isolation technology

Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Toshihiko Himeno; Ken Takeuchi; Tamio Ikehashi; Kazushige Kanda; Koji Hosono; Riichiro Shirota; Seiichi Aritome; Kazuhiro Shimizu; Kazuo Hatakeyama; Koji Sakui

Higher density flash memories for mass storage are attractive for application in the audio-video field, for example, in digital cameras and for voice recording. A 100 MB Flash records one hour CD-quality music. Improvements in video compression techniques are expected to realize gigabyte flash, enabling movies on silicon in the near future; a development that is expected to lead to rapidly rising demand for high-density flash. Both the low bit cost due to the small cell size and the high program and read performance are important factors for the high density flash. A NAND flash has potential advantages in those respects. Shallow trench isolation (STI) shrinks bit line pitch to 73% of that in the case of conventional LOCOS isolation, enabling 0.29 um/sup 2/ cell 0.25 /spl mu/m design rules. The 129.76 mm/sup 2/ chip is made possible by using NAND type memory cell and STI.


international solid-state circuits conference | 1995

A 35 ns cycle time 3.3 V only 32 Mb NAND flash EEPROM

Yoshihisa Iwata; Kenichi Imamiya; Yoshihisa Sugiura; Hiroshi Nakamura; Hideko Oodaira; Masaki Momodomi; Yasuo Itoh; T. Watanabe; H. Araki; Kazuhito Narita; K. Masuda; J.-I. Miyamoto

A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.


Archive | 1998

Shielded bit line sensing scheme for nonvolatile semiconductor memory

Yoshihisa Sugiura; Yoshihisa Iwata; Hiroshi Watanabe


Archive | 2005

Non-volatile memory system having a pseudo pass function

Yoshihisa Sugiura; Tatsuya Tanaka; Atsushi Inoue


Archive | 1993

Non-volatile semiconductor memory device with high voltage generator

Yasuo Itoh; Sumio Tanaka; Junichi Miyamoto; Hiroshi Nakamura; Yoshihisa Iwata; Kenichi Imamiya; Yoshihisa Sugiura


Archive | 1998

Multi-level nonvolatile semiconductor memory device

Yoshihisa Sugiura; Tamio Ikehashi


Archive | 2000

Non-volatile semiconductor memory device and data erase controlling method for use therein

Toshio Yamamura; Yoshihisa Sugiura; Kazuhisa Kanazawa; Koji Sakui; Hiroshi Nakamura


Archive | 2007

Semiconductor integrated circuit device and non-volatile memory system using the same

Atsushi Inoue; Yoshihisa Sugiura; Tatsuya Tanaka


Archive | 1999

Semiconductor integrated circuit having active mode and standby mode converters

Tamio Ikehashi; Yoshihisa Sugiura; Kenichi Imamiya; Ken Takeuchi; Yoshihisa Iwata


Archive | 2005

Non-volatile memory system

Yoshihisa Sugiura; Tatsuya Tanaka; Atsushi Inoue

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