Yoshiyuki Ishigaki

A C-switch cell for low-voltage and high-density SRAMs

We propose a novel static random access memory (SRAM) cell named complementary-switch (C-switch) cell. The proposed SRAM cell features: (1) C-switch in which an n-channel bulk transistor and a p-channel TFT are combined in parallel; (2) single-bit-line architecture; (3) gate-all-around TFT (GAT) with large ON-current of /spl mu/A order. With these three features, the proposed cell enjoys stability at 1.5 V and is 16% smaller in size than conventional cells. The C-switch cell is built with only a triple poly-Si and one metal process using 0.3 /spl mu/m design rules.

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy

A 7-Mb BiCMOS ECL (emitter coupled logic) SRAM was fabricated in a 0.8 mu m BiCMOS process. An improved buffer with a high-level output of nearly V/sub CC/ is adopted to eliminate the DC current in the level converter circuit, and the PMOS transistor has a wide operating margin in the level converter. The configurable bit organization is realized by using a sense-amplifier switch circuit with no access degradation. A wired-OR demultiplexer for the *1 output, having the same critical path as the *4 output circuit, allows for the same access time between the two modes. The *1 or *4 mode is electrically selected by the external signal. A simplified programming redundancy technology, shift redundancy, is utilized. Address programming is performed by cutting only one fuse in the shift redundancy. The RAM operates at the ECL-10K level with an access time of 7 ns. and the power dissipation at 50 MHz is 600 mW for the * mode. >

Suppression of hot carrier effects by laterally graded emitter (LGE) structure in BiCMOS

A novel device structure, called a laterally graded emitter LGE structure, is studied for high-reliability BiCMOS LSI. In the LGE structure, by adding a low-impurity concentration region (N/sup -/ region) near the surface to the N/sup +/ emitter, the peak electric field between emitter and base in reduced and hot carrier effects due to the reverse bias of the emitter-base junction are suppressed. The optimized N/sup -/ emitter maintains the high performance of a bipolar transistor and improves the tolerance against the reverse bias stress.<<ETX>>

A C-Switch cell for low-voltage operation and high-density SRAMs

We propose a novel single-bit-line SRAM cell called a Complementary-Switch (C-Switch) cell. This cell features a C-Switch which combines an n-channel bulk transistor and a p-channel TFT in parallel. Through the use of a single-bit-line architecture with the C-Switch and a high performance TFT called Gate-All-around TFT (GAT), the proposed cell achieves both stable operation at 1.5 V and a size reduction of 16% when compared to conventional structures. Moreover, we have realized this cell using only a triple poly-Si and one metal process on a 0.3 /spl mu/m design rule.

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8- mu m BiCMOS technology. >

New bit line architecture for ultra high speed SRAMs-T-shaped bit line and its real application to 256 k BiCMOS TTL SRAM

The authors propose a novel bit line architecture, the T-shaped bit line architecture (TSBA), which is suitable for high-speed, high-density and/or large bit-wide configuration SRAMs (static random-access memories). This architecture is applied to 256-kb BiCMOS TTL (transistor-transistor logic) I/O SRAM with a typical access time of 5.8 ns. To achieve sub-6-ns access time, a bipolar Darlington column sense amplifier, a global column decode technique, a shielded data bus technique with TSBA, and 0.8- mu m BiCMOS technology are employed.<<ETX>>