Young-Kuk Kim

Bulk synthesis of ordered macroporous silica particles for superhydrophobic coatings.

We report the bulk synthesis of ordered macroporous ceramic particles by the emulsion templating process. Large polystyrene (PS) beads and small silica nanoparticles were assembled simultaneously inside an emulsion, which formed composite structured particles during the evaporation of droplets. Then, by burning out PS beads, macroporous ceramic particle films were produced on substrate. The size of ordered macroporous particles could be controlled by adjusting the emulsification condition for confining emulsions. As well, the pore size could be controlled by changing the diameter of PS beads. The surface of the ordered macroporous particle films was coated with fluorinated molecules, which have shown superhydrophobic property due to multi-scale roughness.

One-Dimensional Thickness Scaling Study of Phase Change Material

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (<i>V</i>_th), <i>V</i>_th drift, high resistance state (RESET) resistance (<i>R</i>_RESET) drift, and crystallization temperature (<i>T</i>_crys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. <i>V</i>_th scales down to 0.65-0.5 V (at 25°C-75°C) for 6-nm-thick Ge₂Sb₂Te₅ (GST), showing that stable read operation is possible in scaled PCM devices. The <i>V</i>_th drift measurement suggests that <i>V</i>_th drift can be attributed to threshold switching field (<i>E</i>_th) drift, whereas <i>V</i>_th0, i.e., <i>V</i>_th at zero thickness, stays almost constant. <i>R</i>_RESET drift shows no dependence on the amorphous GST thickness. <i>T</i>_crys is ~175°C for the device with 6-nm-thick GST, compared with ~145°C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM.

(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})

1D thickness scaling study on a-GST has been successfully demonstrated without the help of ultra-fine lithography. Vth linearly scales down to ∼0.65 V at 6 nm scale, showing that stable read operation is possible at elevated temperature (70 °C). Reset R drift shows no dependency on the a-GST thickness up to 6 nm regime. Thin a-GST shows enhanced thermal stability compared to thick a-GST.

Using a Pseudo 3-Terminal Device

A novel LOCOS type isolation technology, Nitride Cladded Poly-Si Spacer LOGOS (NCPSL) which is for the 1 giga bit DRAM, has been developed. The features of the NCPSL process are low birds beak encroachment and long effective isolation length, which are achieved by using substrate silicon recess etching, poly-Si sidewall spacer, and selectively deposited SiN to the poly-Si spacer. NCPSL isolation shows the excellent active definition, high punchthrough voltage, low junction leakage current, hump free transistor characteristic, and good gate oxide integrity. Considering its isolation characteristics, NCPSL is the very practical technology for the isolation of 1 giga bit DRAM.