Soonoh Park

Full Integration of Highly Manufacturable 512Mb PRAM based on 90nm Technology

Fully functional 512Mb PRAM with 0.047mum2 (5.8F2) cell size was successfully fabricated using 90nm diode technology in which the authors developed novel process schemes such as vertical diode as cell switch, self-aligned bottom electrode contact scheme, and line-type Ge2Sb2Te5. The 512Mb PRAM showed excellent electrical properties of sufficiently large on-current and stable phase transition behavior. The reliability of the 512Mb chip was also evaluated as a write-endurance over 1E5 cycles and a data retention time over 10 years at 85degC

Novel Heat Dissipating Cell Scheme for Improving a Reset Distribution in a 512M Phase-change Random Access Memory (PRAM)

Programming with larger current than optimized one is often preferable to ensure a good resistance distribution of high-resistive reset state in high-density phase-change random access memories because it is very effective to increase the resistance of cells to a target value. In this paper, we firstly report that this larger current writing may conversely degrade the reset distribution by reducing the resistance of normal cells via the partial crystallization of amorphous Ge2Sb2Te5 and this degradation can be suppressed by designing a novel cell structure with a heat dissipating layer.

One-Dimensional Thickness Scaling Study of Phase Change Material

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (<i>V</i>_th), <i>V</i>_th drift, high resistance state (RESET) resistance (<i>R</i>_RESET) drift, and crystallization temperature (<i>T</i>_crys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. <i>V</i>_th scales down to 0.65-0.5 V (at 25°C-75°C) for 6-nm-thick Ge₂Sb₂Te₅ (GST), showing that stable read operation is possible in scaled PCM devices. The <i>V</i>_th drift measurement suggests that <i>V</i>_th drift can be attributed to threshold switching field (<i>E</i>_th) drift, whereas <i>V</i>_th0, i.e., <i>V</i>_th at zero thickness, stays almost constant. <i>R</i>_RESET drift shows no dependence on the amorphous GST thickness. <i>T</i>_crys is ~175°C for the device with 6-nm-thick GST, compared with ~145°C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM.

(\hbox{Ge}_{2}\hbox{Sb}_{2}\hbox{Te}_{5})

1D thickness scaling study on a-GST has been successfully demonstrated without the help of ultra-fine lithography. Vth linearly scales down to ∼0.65 V at 6 nm scale, showing that stable read operation is possible at elevated temperature (70 °C). Reset R drift shows no dependency on the a-GST thickness up to 6 nm regime. Thin a-GST shows enhanced thermal stability compared to thick a-GST.

Using a Pseudo 3-Terminal Device

Effects of ozone treatment and charged defects on retention characteristics of Ir/IrO2/Pb(Zr, Ti)O3 (PZT)/Pt/IrO2/Ir capacitors were systematically investigated. For these purposes, PZT thin films were exposed to ozone environment to promote enhanced surface oxidation. After baking the Ir/IrO2/PZT/Pt/IrO2/Ir capacitors at 125°C for 500 h, degradation of Qnv (non-volatile charge) value of the ozone-treated capacitors was approximately 17.6%, that is less than one fifth of that of the untreated capacitors. X-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) studies showed that the amount of oxygen-vacancies near the PZT surface was dramatically decreased by the ozone treatment. The Schottky barrier height of the ozone-treated capacitors increased when compared to that of the untreated capacitors (the Schottky barrier height of the untreated and the ozone-treated capacitor was 0.29 eV and 0.43 eV, respectively). Therefore, one can conclude that the retention characteristics seem to be closely associated with oxygen related defects near the ferroelectric/electrode interface and the control of the interface properties of PZT thin film is a key technology to pursue reliable function characteristics of ferroelectric random access memory (FRAM) devices.

1D thickness scaling study of phase change material (Ge 2 Sb 2 Te 5 ) using a pseudo 3-terminal device

We fabricated trench PbZrxTi1-xO3 (PZT) capacitors that can be used in 256Mbit 1T-1C FRAM devices. The capacitor has 0.25mum diameter and 0.4mum depth. Three layers, Ir(20nm)/PZT(60nm)/Ir(20nm), were deposited in SiO2 trench holes by ALD and MOCVD. Both columnar and granular grains were formed on the sidewalls of the trench capacitors, and their relative portion had strong size dependence. The trench capacitors with more columnar PZT grains showed good switching behavior under 2.1V external bias and 19 to 24 muC/cm2 remnant polarization

Enhanced Retention Characteristics of Pb(Zr, Ti)O3 Capacitors by Ozone Treatment

We investigated a novel technique of modifying the interface between a Pb(ZrxTi1-x)O3 (PZT) thin film and electrodes for high density 64 Mbit ferroelectric random access memory (FRAM) device. Using a SrRuO3 buffer layer, we successfully developed highly reliable 0.15 µm/14 F2 cell FRAM capacitors with 75-nm-thick polycrystalline PZT thin films. The SrRuO3 buffer layer greatly enhanced ferroelectric characteristics due to the decrease in interfacial defect density. In PZT capacitors with a total thickness of 180 nm for whole capacitor stack, a remnant polarization of approximately 42 µC/cm2 was measured with a 1.4 V operation. In addition, an opposite state remnant polarization loss of less than 15% was observed after baking at 150 °C for 100 h. In particular, we found that the SrRuO3 buffer layer also played a key role in inhibiting the diffusion of Pb and O from the PZT thin films.

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Metal organic chemical vapor deposition (MOCVD) of Pb(ZrxTi1-x)O3 (PZT) and its capacitor module process were established for ferroelectric memory device integration. The 130 nm-thick PZT films were deposited on Ir layers at 530°C or 550°C. The remnant polarization of the Ir/IrO2/PZT/Ir capacitors is in the range of 15 to 21 µC/cm2, and their leakage current is 10-5 A/cm2 at 2.5 V without additional annealing. The degradation in their switching endurance is less than 5% after 1010 cycles, indicating that the interfaces formed between the PZT and Ir layers can be optimized to improve their fatigue properties. To evaluate the capacitors on the devices, the conventional backend process was performed after encapsulating the capacitors with AlOx/TiOx layers located on the poly-Si plug. High charge separation and fully functional bit activities were obtained, demonstrating that this MOCVD-PZT process is a reliable integration scheme for high-density ferroelectric memory devices.

Highly reliable 0.15 μm/14 F2 cell ferroelectric random access memory capacitor using SrRuO3 buffer layer

ABSTRACT We successfully developed 256Mb Phase Change Random Access Memory (PRAM) based on 0.10μ m-CMOS technologies using ring type contact. The writing current with uniform CD process variation of Bottom Electrode Contact (BEC) was achieved by improving CMP process and developing core dielectric material. Also, the ring type contact scheme provided strong reliability such as the cycling endurance and data retention time for 256 Mb high density PRAM.

Integration of ferroelectric random access memory devices with Ir/IrO2/Pb(ZrxTi1-x)O3/Ir capacitors formed by metalorganic chemical vapor deposition-grown Pb(ZrxTi1-x)O3

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 µC/cm2 measured at 3 V.