Yu-Lien Huang

High density 3D integration using CMOS foundry technologies for 28 nm node and beyond

Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (TSV), wiring and redistribution layer (RDL), wafer thinning and handling, micro-bump (µ-bump) processes and joining, that form the building blocks for 3D IC technology were developed based on established Si foundry technologies. Test vehicles (TVs) have been designed to develop and optimize the processes, structures, as well as to evaluate the performance, yield and reliability of the 3D integration scheme.

A 25-nm gate-length FinFET transistor module for 32nm node

FinFET is the most promising double-gate transistor architecture [1] to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 µA/µm drive current respectively at 100nA/µm leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.