Yuji Yatsuda

Scaling Down MNOS Nonvolatile Memory Devices

Scaling down of MNOS nonvolatile memory devices are presented. Knowledge of operating mechanisms of the electrically alterable nonvolatile memory provides guidelines for choosing the proper thickness of the gate insulating films (Si3N4 and SiO2). It is found that writing time of an MNOS device depends on the nitride thickness alone but not on the oxide thickness, while erasing time depends on the thicknesses of both films. A 10-V programmable scaled down MNOS memory device is realized by decreasing nitride thickness from 50 nm to 19.5 nm and keeping oxide thickness almost constant at about 2.1 nm. Experimental devices are shown to be highly reliable, if the Si3N4 is slightly oxidized, resulting in an MONOS structure.

Hi-MNOS II technology for a 64-kbit byte-erasable 5-V-only EEPROM

Improved high-performance MNOS (HiMNOS II) technology has been developed for application to a byte-erasable 5-V only 64-kbit EEPROM. A minimum feature size of 2 µm and scaling theory implementation for the MNOS device have led to the realization of a small cell size of 180 µm2, a low programming voltage of 16 V, and a high packing density of 64 kbits. The high-voltage structure of the MNOS device, as well as the high-voltage circuit technology, has been developed to eliminate dc programming current in the memory array and the high-voltage switching circuits for the use of on-chip generated programming voltage. This voltage is regulated with an accuracy of ± 1 V by using a Zener diode formed in a p-type well. Moreover, in order to accomplish reliable byte erasing, high-voltage switching circuits and their control logic have been carefully designed so as to eliminate the possibility of erroneous writing or erasing due to a timing skew of the high-voltage application to the memory cells. The obtained 64K EEPROM chip shows such superior characteristics as a fast access time of 150 ns, low power dissipation of 55 mA, high-speed write and erase times of less than 1 ms, and high endurance of less than 1-percent failure after 104write/erase cycles.

n-channel Si-gate MNOS Device for High Speed EAROM

New technologies for high speed and high performance electrically alterable read-only memories are developed. The memory cell consists of an n-channel silicon gate MNOS device and a switching transistor (two devices per bit). This cell configuration and advanced processing technologies realize high speed, no read-cycle limitations, long data retention and high packing density for n-channel EAROMs when compared to conventional p-channel aluminum gate EAROMs. The features of the new MNOS transistors are investigated and capability of ten year unpowered data storage at 125°C is confirmed. Write and erase times are 100 µs and several ms at 25 V, respectively. A single 5 V 2 k-bit EAROM with complete peripheral circuits is also fabricated. The measured access time is about 100 ns, which is more than five times faster than conventional EAROMs.

An advanced MNOS memory device for highly-integrated byte-erasable 5V-only EEPROMs

An advanced MNOS memory device promising the next-stage, high-density, byte-erasable, 5V-only EEPROM is described. The advanced device features: (1) dimensions that, except for an ultrathin oxide thickness, are reduced in proportion to program voltage, (2) a high drain breakdown voltage obtained by a newly developed high voltage structure with n and n+ drain regions and thick oxide over the n regions. This structure is free from any decrease in program inhibiting voltage or internally boosted voltage that causes serious problems in reliability. The feasibility of shrunk MNOS devices is strongly confirmed in LSI levels, as well as in discrete MNOS devices, by testing not only discrete devices but also low-program-voltage versions of the 16K-bit EEPROM incorporating shrunk MNOS devices. A 20V breakdown voltage is obtained in high-voltage-structure MNOS devices. This is about 10V greater than that of fully self-aligned-structure MNOS devices.