Yuki Ikku

Formation of III?V-on-insulator structures on Si by direct wafer bonding

We have studied the formation of III?V-compound-semiconductors-on-insulator (III?V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III?V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O2?plasma-assisted DWB process with ECR sputtered SiO2?BOX layers and a DWB process based on atomic-layer-deposition Al2O3?(ALD-Al2O3) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO2?and ALD-Al2O3?BOX layers are desorption of Ar and H2O gas, respectively. In order to suppress micro-void generation in the ECR-SiO2?BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al2O3?BOX layers to increase the deposition temperature of the ALD-Al2O3?BOX layers. It is also another possible solution to deposit ALD-Al2O3?BOX layers on thermally oxidized SiO2?layers, which can absorb the desorption gas from ALD-Al2O3?BOX layers.

Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors

Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high device performance as well as merging electrical and photonic applications on the Si platform. Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300 mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.

High performance InGaAs-on-insulator MOSFETs on Si by novel direct wafer bonding technology applicable to large wafer size Si

In this paper, we present first demonstration of InGaAs-on-insulator (-OI) MOSFETs with wafer size scalability up to Si wafer size of 300 mm and larger by direct wafer bonding (DWB) process using InGaAs channels grown on 4-inch Si donor substrates with III-V buffer layers instead of InP donor substrates. It is found that this DWB process can provide the high quality InGaAs thin films on Si. The fabricated InGaAs-OI MOSFETs exhibited the high electron mobility of 1700 cm2/Vs and large mobility enhancement of 3 × against Si MOSFETs.

Surface Leakage Reduction in MSM InGaAs Photodetector on III–V CMOS Photonics Platform

By evaluating the leakage current components of Ni/InGaAs Schottky junctions, we have revealed that the surface leakage current was dominant in the dark current of the waveguide metal-semiconductor-metal (MSM) InGaAs photodetector (PD) fabricated on the III-V CMOS photonics platform. To suppress the surface leakage, we have investigated the impact of the InAlAs Schottky barrier enhancement (SBE) layer on the surface leakage. It is found that the surface leakage can be significantly reduced by the surface passivation effect of the InAlAs SBE layer in addition to the reduction in the junction bulk leakage. We have also found that the surface passivation by an improper oxide such as Al2O3 on the SBE layer increased the dark current probably due to the fixed charges in the oxide layer. By introducing the InP/InAlAs SBE layer without any oxide passivation, we have successfully demonstrated the low-darkcurrent MSM InGaAs PD which was monolithically integrated with an InP photonic-wire waveguide fabricated on a III-V-on-insulator wafer. When a bias voltage of 1 V was applied, the dark current of 7 nA was obtained with 0.15 A/W responsivity for a 1550-nm wavelength.

Low-dark-current waveguide InGaAs metal–semiconductor–metal photodetector monolithically integrated with InP grating coupler on III–V CMOS photonics platform

The fabrication of waveguide InGaAs metal–semiconductor–metal (MSM) photodetector (PD) monolithically integrated with an InP grating coupler has been demonstrated using the III–V CMOS photonics platform. The grating coupler shows approximately 28% coupling efficiency, which allows wafer-scale testing with better coupling and alignment tolerance than edge-fire coupling. The InGaAs PD with an InP/InAlAs Schottky barrier enhancement (SBE) layer exhibits a low dark current of 0.75 nA at 1 V bias. When the bias is 4 V, a responsivity of approximately 0.19 A/W with 3 nA dark current is achieved. The fabricated PD on a III–V-on-insulator wafer can be used for the fabrication of low-power receiver chips for optical interconnects.

Physical understanding of electron mobility in asymmetrically strained InGaAs-on-insulator metal-oxide-semiconductor field-effect transistors fabricated by lateral strain relaxation

In this paper, we fabricated asymmetrically tensile-strained In0.53Ga0.47As-on-insulator (-OI) metal-oxide-semiconductor field-effect transistors (MOSFETs) using a lateral strain relaxation technique. A stripe-like line structure, fabricated in biaxially strained In0.53Ga0.47As-OI can lead to the lateral strain relaxation and asymmetric strain configuration in In0.53Ga0.47As-OI with the channel width of 100 nm. We have found that the effective mobility (μeff) enhancement in In0.53Ga0.47As-OI MOSFETs with uniaxial-like asymmetric strain becomes smaller than that in In0.53Ga0.47As-OI MOSFETs with biaxial strain. We have clarified from a systematic analysis between the strain values and the μeff characteristics that this mobility behavior can be understood by the change of the energy level of the conduction band minimum due to the lateral strain relaxation.

Heterogeneous CMOS Photonics Based on SiGe/Ge and III–V Semiconductors Integrated on Si Platform

The heterogeneous integration of SiGe, Ge, and III–V semiconductors on Si provides many opportunities to develop high-performance photonic integrated circuits through complementary metal oxide semiconductor (CMOS) processes. We found that strained SiGe possesses greater free-carrier effects than Si, contributing to the improved modulation efficiency of Si-based optical modulators. In addition to low-dark-current Ge photodetectors (PDs) with GeO 2 passivation, we investigated Ge CMOS photonics platform for midinfrared wavelengths. We demonstrated Ge passive waveguides and carrier-injection variable optical attenuators (VOAs) on a Ge-on-insulator wafer. We also investigated III–V CMOS photonics platform on a III–V-on-insulator (III–V-OI) wafer. The strong optical confinement in the III–V-OI structure enabled the realization of ultrasmall III–V passive waveguides similarly to those in Si photonics. Carrier-injection InGaAsP optical switches and VOAs as well as InGaAs waveguide PDs were also demonstrated on III–V-OI wafers. We discuss the opportunities and challenges of heterogeneous CMOS photonics technologies to develop high-performance electronic–photonic integrated circuits for near-infrared and midinfrared applications.

Effect of III–V on insulator structure on quantum well intermixing

To achieve the monolithic active/passive integration on the III–V CMOS photonics platform, quantum well intermixing (QWI) on III–V on insulator (III–V-OI) is studied for fabricating multi-bandgap III–V-OI wafers. By optimizing the QWI condition for a 250-nm-thick III–V layer, which contains a five-layer InGaAsP-based multi-quantum well (MQW) with 80-nm-thick indium phosphide (InP) cladding layers, we have successfully achieved a photoluminescence (PL) peak shift of over 100 nm on the III–V-OI wafer. We have also found that the progress of QWI on the III–V-OI wafer is slower than that on the InP bulk wafer regardless of the buried oxide (BOX) thickness, bonding interface materials, and handle wafers. We have also found that the progress of QWI on the III–V-OI wafer is slower than that on the InP bulk wafer regardless of the buried oxide (BOX) thickness, bonding interface materials, and bulk support wafers on which the III–V-OI structure is formed (handle wafers). By comparing between the measured PL shift and simulated diffusions of phosphorus vacancies and interstitials during QWI, we have found that the slow QWI progress in the III–V-OI wafer is probably attributed to the enhanced recombination of vacancies and interstitials by the diffusion blocking of vacancies and interstitials at the BOX interface.

CMOS photonics technologies based on heterogeneous integration of SiGe/Ge and III-V on Si

In this paper, we present heterogeneous integration of SiGe/Ge and III-V semiconductors on Si for electronic-photonic integrated circuits through CMOS photonics technologies. The introduction of high-mobility channel materials, which is promising for achieving high-performance MOSFETs, are also beneficial to photonics for off-chip/on-chip optical interconnection and bio/medical sensors. As for SiGe CMOS photonics, strained SiGe is shown to enhance modulation efficiency for optical modulators. We demonstrated that the plasma dispersion effect is enhanced by strain application to SiGe owing to a decrease in the effective hole mass. As for Ge CMOS photonics, Ge-based photonic-wire waveguides are demonstrated for Mid-IR applications by using photonic Ge-on-Insulator wafers for the first time. As for III-V CMOS photonics, we developed high-quality photonic III-V on Insulator wafers by using direct wafer bonding. InGaAsP photonic-wire devices including optical switches and InGaAs photodetectors are demonstrated. We have also successfully demonstrated wafer-size-scalable III-V-OI wafers by using a III-V epi on Si wafer.

Multi-bandgap III-V on insulator wafer fabricated by quantum well intermixing for III-V CMOS photonics platform

We have investigated a fabrication procedure of a multi-bandgap III-V on insulator (III-V-OI) wafer by quantum well intermixing for active/passive integration on III-V CMOS photonics platform. We have sucessfully achieved approximately 50-nm wavelength shift in photoluminecense peak on the III-V-OI wafer by P impantation with 40 keV implant energy.