Yung Fu Chong

Laser thermal processing of amorphous silicon gates to reduce poly-depletion in CMOS devices

One major challenge in advanced CMOS technology is to have adequate dopant activation at the polycrystalline silicon (poly-Si) gate/gate oxide interface to minimize the poly-Si depletion effect. In this paper, laser thermal processing (LTP) was employed to fabricate single or dual-layer poly-Si-gated MOS capacitors with ultrathin gate oxides. Capacitance-voltage data show that the carrier concentration at the poly-Si gate/gate oxide interface increases substantially when the devices are subjected to LTP prior to a rapid thermal anneal (RTA). Thus, LTP readily reduces the poly-depletion thickness in MOS devices. For p/sup +/-gated capacitors, this is achieved with boron penetration that is equivalent to the control sample with 1000/spl deg/C, 5 s RTA (without LTP). In addition, results from secondary ion mass spectrometry indicate that the concentration of dopants near the critical gate/gate oxide interface increases significantly after a post-LTP anneal, in good agreement with the electrical data. Time-dependent dielectric breakdown studies show that the gate oxide reliability is not degraded even after LTP at high fluences.

Evaluation of back-side secondary ion mass spectrometry for boron diffusion in silicon and silicon-on-insulator substrates

We present a study on the redistribution of boron in (100) crystalline silicon and silicon-on-insulator (SOI) substrates after rapid thermal processing (RTP). The use of SOI back-side secondary ion mass spectrometry (SIMS) technique in obtaining an accurate diffusion profile is also investigated. Our results show that the boron diffusion profiles (using conventional frontside SIMS) do not deviate in any of the two types of substrates after RTP with a soak time of 30sec, indicating that the insulating effect of SOI substrate does not enhance the diffusion of boron. Since the profile obtained by the back-side SIMS technique is always shallower than that of front-side SIMS, it is deduced that the back-side SIMS technique gives a better representation of the real profile.

Time-resolved reflectance studies of silicon during laser thermal processing of amorphous silicon gates on ultrathin gate oxides

In this paper, we report the systematic investigation on the melt characteristics of silicon during laser thermal processing (LTP) of amorphous silicon (a-Si) gates on ultrathin gate oxides. LTP is used to reduce the gate depletion effect in advanced semiconductor devices. The influence of implantation-induced damage and chemical inhomogeneities on the melt behavior of ion-implanted a-Si is studied using in situ time-resolved reflectance (TRR) measurements and ex situ secondary ion mass spectrometry. The results from TRR measurements indicate the presence of a buried melt for a-Si implanted with B+ at a subamorphizing dose. In contrast, such a melt behavior is not observed during LTP of undoped a-Si and a-Si implanted with As+ at an amorphizing dose. We attribute the marked difference in the melt characteristics to the competitive effects between compositional inhomogeneities and the extent of amorphization in the a-Si layer. It should be noted that the as-deposited a-Si gate is not really “amorphous” in ...

Grain size analysis of C54–TiSi2 under different processing conditions for deep-submicron polycrystalline silicon gate length

The effect of preamorphization using silicon (Si) ion, different annealing temperatures and heating rates on nucleation density and grain size of C49 and C54–TiSi2 have been studied. The average grain size of C54–TiSi2 is found to decrease when the peak annealing temperature is changed from 700 to 850u200a°C. We found that the nucleation threshold temperature is about 900u200a°C at which the C54–TiSi2 grain size levels off at about 23 nm. We also found that the grain size of C54–TiSi2 is independent of different heating rates. Our results also show that preamorphization is not so effective in reducing the C54–TiSi2 grains when annealing temperature is raised to above 850u200a°C. However, preamorphization does improve the grain size uniformity. By optimizing the processing parameters such as peak annealing temperature, heating rates and preamorphization, we have demonstrated the formation of C54–TiSi2 on 0.12 μm polycrystalline silicon (polysilicon) lines with no agglomeration.