Yusuke Kasahara

Directed self-assembly lithography using coordinated line epitaxy (COOL) process

In this study, half-pitch (HP) 15 nm line-and-space (L/S) metal wires were successfully fabricated and fully integrated on a 300 mm wafer by applying directed self-assembly (DSA) lithography and pattern transfer for semiconductor device manufacturing. In order to evaluate process performances of DSA, we developed a simple sub-15 nm L/S patterning process using polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) lamellar block copolymer (BCP), which utilizes trimming resist and shallow etching spin-on-glass (SOG) as pinning guide[1]-[4]. From the results of defect inspection after SOG etch using Electron Beam (EB) inspection system, defects were classified as typical DSA defects or defects relating to DSA pattern transfer. From the evaluation of DSA L/S pattern Critical Dimension (CD), roughness and local placement error using CD-SEM, it is considered that isolated PS lines are placed at the centerline between guides and that placement of paired PS lines depends on the guide width. The control of the guide resist CD is the key to local placement error and the paired lines adjacent to the guide shifted toward the outside (0.5 nm) along the centerline of the isolated line after SOG etch. We demonstrated fabrication of HP 15 nm metal wires in trenches formed by the DSA process with reactive ion etching (RIE), followed by metal chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). By SEM observation of alignment errors between the trenches and connect spaces, overlay shift patterns (-4 nm) in guide lithography mask were fabricated without intra-wafer alignment errors.

Defect-aware process margin for chemo-epitaxial directed self-assembly lithography using simulation method based on self-consistent field theory

We proposed a new concept of “defect-aware process margin.” Defect-aware process margin was evaluated by investigating the energy difference between the free-energy of the most stable state and that of the first metastable state. The energy difference is strongly related to the defect density in DSA process. As a result of our rigorous simulations, the process margin of the pinning layer width was found to be: (1) worse when the pinning layer affinity is too large, (2) better when the background affinity has the opposite sign of the pinning layer affinity, and (3) better when the top of the background layer is higher than that of the pinning layer by 0.1L0.

RIE challenges for sub-15 nm line-and-space patterning using directed self-assembly lithography with coordinated line epitaxy (COOL) process

Directed self-assembly (DSA) is one of the promising candidates for next-generation lithography. We developed a novel simple sub-15 nm line-and-space (L/S) patterning process, the “coordinated line epitaxy (COOL) process,” using grapho- and chemo-hybrid epitaxy. In this study we evaluate the DSA L/S pattern transfer margin. Since defect reduction is difficult in the case of the DSA pattern transfer process, there is a need to increase the pattern transfer margin. We also describe process integration for electrical yield verification.

Electrical yield verification of half-pitch 15 nm patterns using directed self-assembly of polystyrene-block-poly(methyl methacrylate)

A novel half-pitch (HP) 15 nm line pattern multiplication process with simple process steps and low cost-of-ownership using a polystyrene-block-poly(methyl methacrylate) lamellar block copolymer was developed to carry out process verification of directed self-assembly lithography on a 300 mm wafer for practical semiconductor device manufacturing. Electrical yield verification of HP 15 nm metal wire circuits fabricated by the HP 15 nm line pattern multiplication process was carried out on a 300 mm wafer. The electrical yield verification revealed the viability of the HP 15 nm line pattern multiplication process from the perspective of the total practical performance including critical dimension control, defect control, local placement error, line width roughness, line edge roughness, and process windows in the pattern transfer process.

A simulation study on bridge defects in lamellae-forming diblock copolymers

In this paper we will describe a self-consistent field theory simulation study on bridge defects in lamellae-forming diblock copolymers. Because the bridge defects are buried three-dimensional defects formed in the diblock copolymer film, it is difficult to observe and determine what causes them. To determine the cause of the bridge defects effectively, self-consistent field theory simulations were used. By reproducing structural characteristics of the bridge defects in the simulation, the cause of the bridge defects were clarified. Finally, we discussed ways to prevent the bridge defects.

Defect dynamics in directed self-assembly of block copolymers (Conference Presentation)

Directed self-assembly (DSA) of block copolymers (BCPs) is a lithographic technique that is expected to be mutually complimentary with ArF immersion lithography, EUV lithography, electron beam direct writing, or nanoimprint for sub-15 nm line patterning and sub-20 nm contact hole patterning. Defect mitigation is the primary challenge behind the use of DSA lithography in practical applications in advanced semiconductor device manufacturing. Therefore, resolve this issue, defect dynamics needs to be clarified using in-situ measurements of self-assembling processes of BCPs in conjunction with modeling approaches. In this work, the evolution of a surface morphology in self-assembling processes of BCPs during annealing was investigated using in-situ atomic force microscope (AFM).5 A JPK NanoWizard ULTRA Speed AFM (JPK Instruments AG) under AC mode (lock-in phase signal image) was employed to carry out in-situ measurements of self-assembling of symmetrical polystyrene-block-poly(methyl methacrylate) (PS-b-PMMA) thin films with a thickness of 40 nm, and a domain spacing 30 nm domain spacing (L0) of 30 nm on a 5 nm thick neutral layer (PS-r-PMMA) during the thermal annealing process starting from a disordered as-cast state. The COOrdinated Line epitaxy (COOL) process was applied to provide DSA line multiplication patterns as hybrid guide patterns which act as chemical and physical epitaxy process. The in-situ observation approach of the surface morphology during micro-phase separation process revealed the defect generation and rectification processes in DSA thin films. A combination of the time development data in the in-situ AFM and grazing-incidence small-angle X-ray scattering (GI-SAXS) will also be discussed to develop a kinetic modeling for predicting dynamical changes in the three-dimensional nanostructures.

Nano-defect management in directed self-assembly of block copolymers (Conference Presentation)

Directed self-assembly (DSA) of block copolymers (BCPs) has been expected to become one of the most promising next generation lithography candidates for sub-15 nm line patterning and sub-20 nm contact hole patterning. In order to provide the DSA lithography to practical use in advanced semiconductor device manufacturing, defect mitigation in the DSA materials and processes is the primary challenge. We need to clarify the defect generation mechanism using in-situ measurement of self-assembling processes of BCPs in cooperation with modeling approaches to attain the DSA defect mitigation. In this work, we thus employed in-situ atomic force microscope (AFM) and grazing-incidence small angle X-ray scattering (GI-SAXS) and investigated development of surface morphology as well as internal structure during annealing processes. Figure 1 shows series of the AFM images of PMAPOSS-b-PTFEMA films during annealing processes. The images clearly show that vitrified sponge-like structure without long-range order in as-spun film transforms into lamellar structure and that the long range order of the lamellar structure increases with annealing temperature. It is well-known that ordering processes of BCPs from disordered state in bulk progress via nucleation and growth. In contrary to the case of bulk, the observed processes seem to be spinodal decomposition. This is because the structure in as-spun film is not the concentration fluctuation of disordered state but the vitrified sponge-like structure. The annealing processes induce order-order transition from non-equilibrium ordered-state to the lamellar structure. The surface tension assists the transition and directs the orientation. Figure 2 shows scattering patterns of (a) vicinity of film top and (b) whole sample of the GI-SAXS. We can find vertically oriented lamellar structure in the vicinity of film top while horizontally oriented lamellar structures in the vicinity of film bottom, indicating that the GI-SAXS measurement can clarify the variation of the morphologies in depth direction and that the surface tension affects the orientation of the lamellar structure. Finally a combination of the time development data in the in-situ AFM and the GI-SAXS is used to develop a kinetic modeling for prediction of dynamical change in three-dimensional nano-structures. A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) in Japan under the EIDEC project.

Grapho-epitaxial sub-10nm line and space patterning using lamellar-forming Si-containing block copolymer

Si-rich poly((polyhedral oligomeric silsesquioxane) methacrylate)-b-poly(trifluoroethyl methacrylate) (PMAPOSS-b- PTFEMA) was used to form 8-nm half-pitch line and space (L/S) pattern via grapho-epitaxy. Vertical alignment of the lamellae was achieved without using either a neutral layer or top-coating material. Because PMAPOSS-b-PTFEMA forms vertical lamellae on a variety of substrates, we used two types of physical guide structures for grapho-epitaxy; one was a substrate guide and the other was a guide with an embedded under layer. On the substrate guide structure, a fine L/S pattern was obtained with trench widths equal to 3–7 periods of the lamella spacing of the block copolymer, Lo. However, on the embedded under layer guide structure, L/S pattern was observed only with 3 Lo and 4 Lo in trench width. Cross-sectional transmission electron microscope images revealed that a thick PMAPOSS layer was formed under the PMAPOSS-b-PTFEMA L/S pattern. Pattern transfer of the PMAPOSS-b-PTFEMA L/S pattern was prevented by a thick PMAPOSS layer. To achieve pattern transfer to the under layer, optimization of the surface properties is necessary.

Sub-10nm lines and spaces patterning using grapho-epitaxial directed self-assembly of lamellar block copolymers

Our target at EIDEC is to study the feasibility of directed self-assembly (DSA) technology for semiconductor device manufacturing through electrical yield verification by development of such as process, material, metrology, simulation and design for DSA. We previously developed a grapho/chemo-hybrid coordinated line epitaxial process for sub-15-nm line-and-space (L/S) patterning using polystyrene-block-poly(methyl methacrylate) lamellar block copolymers (BCPs)1– 3. Electrical yield verification results showed that a 30% open yield was successfully achieved with a metal wire line length of 700 μm 4. In the next stage of the evaluation, a sub-10-nm L/S DSA patterning process based on graphoepitaxial DSA of 20-nm lamellar period organic BCPs was developed based on neutral layer and guide space width optimization. At a 30-nm guide height, problems such as BCP overflow and DSA line shorts were observed after the dry development. At a 60-nm guide height, grid-like short defects were observed under dry development shallow etch conditions and sub-10-nm L/S patterns were formed under optimized etch conditions with a suitable BCP film thickness margin. The process performance was evaluated in terms of defects and critical dimension measurements using an electron beam inspection system and critical dimension-scanning electron microscope metrology. The main DSA defects were short defects, and the spatial roughness appeared to be caused by the periodic pitches of these short defects and the guide roughness. We successfully demonstrated the fabrication of sub-10-nm metal wires consists of L/S, pad, connect and cut patterns with controlled alignment and stack structure through lithography, etching and CMP process on a 300- mm wafer using the fully integrated DSA process and damascene processing.

Reactive ion etching challenges for half-pitch sub-10-nm line-and-space pattern fabrication using directed self-assembly lithography

Directed self-assembly is a candidate process for sub-15-nm patterning applications. It will be necessary to develop the DSA process fully and consider process integration to adapt the DSA process for use in semiconductor manufacturing. We investigated the reactive ion etching (RIE) process for the fabrication of sub-10-nm metal wires using the DSA process and the process integration requirements for electrical yield verification. We evaluated the process using an organic high-chi block copolymer (BCP) with a lamellar structure. One critical issue during DSA pattern transfer involves the BCP bottom connection. The BCP bottom connections could be removed without BCP mask loss by using the optimum bias power and the optimum BCP film thickness. The sub-10-nm DSA line-and-space (L/S) patterns were successfully transferred to a SiO2 layer with sufficient film thickness for the fabrication of the metal wire. We also evaluated the overlay technique used in the process. The connect patterns and cut patterns were overlaid on 10-nm trenches fabricated by the DSA process.