Yusuke Morisaki

Low standby power CMOS with HfO/sub 2/ gate oxide for 100-nm generation

We have fabricated 55-nm poly-Si gated n- and p-MOSFETs with HfO/sub 2/ gate dielectric of 3-nm physical thickness deposited by atomic layer deposition (ALD). A conventional CMOS process was used with high-temperature S/D anneal of /spl ges/1000/spl deg/C, cobalt-silicide and pocket implants. The devices showed very promising characteristics for low standby power applications due to drastic reduction of gate leakage current.

Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

The authors found the method to form HfSiON film with an ultrathin SiO/sub 2/ interfacial layer on the Si substrate by oxidizing the HfSiN. The HfSiN film was deposited by using the metal-organic chemical vapor deposition reactor with the shower head, supplying metal (Hf and Si) precursors and NH/sub 3/ gas separately from discharge nozzles. The authors successfully decreased the leakage current of the metal insulator semiconductor diode with HfSiON/SiO/sub 2/ insulator of 1-nm equivalent oxide thickness to 0.036 A/cm/sup 2/ at V/sub fb/-1 V.

Diffusion coefficient of B in HfO/sub 2/

We implanted B ions in a 110-nm-thick HfO/sub 2/ layer, subjected the substrates to various thermal processes, and evaluated the diffusion coefficient by comparing experimental and numerical data. We found that the diffusion coefficient of B in HfO/sub 2/ is higher than that in SiO/sub 2/ by about four orders and almost the same as that in Si. Therefore, the penetration of B through this layer can be expected to be significant, making the use of a cover layer indispensable for p/sup +/ polycrystalline silicon gate devices.

Ultra-thin (T eff inv = 1.7 nm) poly-Si-gated SiN/HfO 2 /SiON high-k stack dielectrics with high thermal stability (1050/spl deg/C)

Demonstrated the high-performance and high-reliability of ultra-thin poly-Si-gated SiN/HfO/sub 2//SiON high-k stack dielectrics. A SiN layer deposited on HfO/sub 2/ is shown to be indispensable to the suppression of the reaction of poly-Si and HfO/sub 2/, resulting in high thermal stability (1050/spl deg/C). This thermally stable SiN/HfO/sub 2//SiON structure can achieve an ultrathin oxide thickness of T/sub eff//sup inv/ (effective oxide thickness measured in strong inversion region) for 1.7 nm, which is less than 1 nm for EOT. A low leakage current of 5 to 6 orders of magnitude lower than that of SiO/sub 2/ was observed. In addition, this thermal stability can lead to high reliability, which includes TDDB and hot electron integrity.

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique can improve carrier mobility and negative bias temperature instability (NBTI). We have confirmed that Ti-doped devices achieve higher performance, and the technique is suitable for 32 nm-technology node and beyond.

Diffusion coefficient of as and P in HfO2

We implanted As and P ions in a 110-nm-thick HfO2 layer, subjected the substrates to various thermal processes, and evaluated their diffusion coefficients by comparing experimental and numerical data. We found that the diffusion coefficients of As and P in HfO2 are almost the same as that of B and are much higher, by two orders, than that of B in SiO2. The impurity penetration through the HfO2 gate insulator is much more severe than that of SiO2 even though a thicker HfO2 layer is available.

Ion implantation impurity profiles in HfO/sub 2/

We implanted B, As, and P ions in a 110-nm-thick layer of HfO/sub 2/ and extracted the parameters of a Pearson IV function. The projected range of the ion implantation was about half of that in SiO/sub 2/. Thus, when impurities were ion implanted in an Si substrate through a thin layer of HfO/sub 2/ or SiO/sub 2/, a smaller dose was retained in the substrate in the former than in the latter case. This effect was demonstrated with P-ion implantation.

Effects of interface oxide layer on HfO 2 gate dielectrics [MISFETS]

We report on the nMISFETs (n-type metal-insulator-semiconductor field effect transistors) characteristics for the atomic layer chemical vapor deposition (ALCVD) HfO/sub 2/ gate stack and the behavior of the HfO/sub 2/ layer during annealing on various oxides.

Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors

We demonstrated for the first time that novel Ni-FUSI process using FLA (Melt-FUSI) dramatically improved both electrical characteristics and cost-benefit performance of LSTP devices. Since the T_inv was aggressively scaled (T_inv = 2.1 nm) with keeping SiON-gate leakage current and increasing hole mobility twice, we achieved the record I_on of 300 muA/mum at the I_off of 20 pA/mum for the pMOS transistor with the L_g of 45 nm at V_d of -1.2 V.