Hiroshi Minakata

Novel multi-bit SONOS type flash memory using a high-k charge trapping layer

We demonstrated SONOS flash memory with a SiO/sub 2//High-k/SiO/sub 2/ structure based on a 2-bit/cell scheme. We evaluated three kinds of high-k dielectric films which were Si/sub 3/N/sub 4/, Al/sub 2/O/sub 3/ and HfO/sub 2/. Among these films, Al/sub 2/O/sub 3/ showed superior retention characteristics. The charge loss amount of Al/sub 2/O/sub 3/ at 150/spl deg/C is almost the same as that of Si/sub 3/N/sub 4/ at 25/spl deg/C. HfO/sub 2/ showed poor retention characteristics. In addition, we have found that each film has a different charge loss mechanism. We speculate that Si/sub 3/N/sub 4/ causes vertical charge migration, Al/sub 2/O/sub 3/ causes scarcely any leakage, and HfO/sub 2/ causes lateral charge migration. As a consequence, Al/sub 2/O/sub 3/ is very suitable for a charge trapping layer in multi-bit SONOS memory.

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

The authors found the method to form HfSiON film with an ultrathin SiO/sub 2/ interfacial layer on the Si substrate by oxidizing the HfSiN. The HfSiN film was deposited by using the metal-organic chemical vapor deposition reactor with the shower head, supplying metal (Hf and Si) precursors and NH/sub 3/ gas separately from discharge nozzles. The authors successfully decreased the leakage current of the metal insulator semiconductor diode with HfSiON/SiO/sub 2/ insulator of 1-nm equivalent oxide thickness to 0.036 A/cm/sup 2/ at V/sub fb/-1 V.

Continuous Growth of Low‐Temperature Si Epitaxial Layer with Heavy Phosphorus and Boron Doping Using Photoepitaxy

The authors grew p{sup +}-n{sup +} silicon epitaxial layers, heavily doped with phosphorus and boron, continuously at 650{degrees}C using low-temperature photoepitaxy. Then N{sup +} photoepitaxial layer with a phosphorus concentration above 10{sup 17} cm{sup {minus}3} grown on p{sup {minus}} substrate shows high-density surface pits, and as a result, poor crystal quality. However, when this n{sup +} photoepitaxial layer is grown continuously on a heavily boron-doped p{sup +} photoepitaxial layer, these surface pits are drastically decreased, disappearing completely above a hole concentration of 10{sup 19} cm{sup {minus}3} in the p{sup +} photoepitaxial layer. The phosphorus activation ratio and electron Hall mobility in the heavily phosphorus-doped n{sup +} photoexpitaxial layer were also greatly improved. The authors investigated the cause of the surface pitting using a scanning transmission electron microscope, secondary ion mass spectroscopy, and energy-dispersive x-ray spectroscopy. They characterized the precipitation of phosphorus atoms on the crystal surface at the initial stage of the heavily phosphorus-doped n{sup +} photoexpitaxial layer growth.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique can improve carrier mobility and negative bias temperature instability (NBTI). We have confirmed that Ti-doped devices achieve higher performance, and the technique is suitable for 32 nm-technology node and beyond.

Continuous growth of heavily doped p+-n+ Si epitaxial layer using low-temperature photoepitaxy

Heavily doped p+ and n+ silicon epitaxial layers were continuously grown at 600 °C using photoenhanced epitaxy. The heavily phosphorus‐doped photoepitaxial layer with a carrier concentration above 1×1017 cm−3 grown on the p− substrate shows very high density surface pits due to phosphorus precipitation, suggesting poor crystal quality. Unexpectedly, when this n+ photoepitaxial layer is continuously grown on a heavily boron‐doped p+ photoepitaxial layer at a boron concentration above 1×1019 cm−3, surface pits completely disappear and crystal quality is greatly improved. The very low growth temperature enabled an extremely abrupt impurity profile to be achieved for the p+‐n+ layer.

Carrier profile designing to suppress systematic V th variation related with device layout by controlling STI-enhanced dopant diffusions correlated with point defects

We directly measured that anisotropic dopant diffusion into the shallow trench isolation (STI) sink was the predominant factor to cause dependence of the threshold voltage (Vth) on the active width along the channel direction (LOD) for the nMOSFETs. We evaluated by Raman spectroscopy and 3-D stress simulation effects of the STI-induced stress variation on the Vth. Moreover, we directly measured that dopant diffusions coupled with point defect, as transient enhanced diffusion, resulted in the carrier profile depending on the LOD. In particular, it was found that the excess point defect in the deep source/drain enhanced the random extension edge roughness and increased intrinsic Vth fluctuation in the narrow-LOD nMOSFET.

Effect of Cap-Metals on Co Salicide Process

A Co salicide process using TiN-cap metal reduces the sheet resistance in narow gate, source and drain regions. However, the detailed mechanism of the cap metal has not been well explained. We investigated various Co salicide processes and clarified the effect of the cap-metal. We found that the Co salicide process without cap-metal was very sensitive to the oxygen, even in very small concentration in the annealing chamber. We found that the cap-metal did not work as a promoter of the silicide reaction through metal stess, but did work mainly as a barrier to oxidation. Using these findings we demonstrated a low sheet resistance in narrow regions down to 0.075 pm with several methods.