Tsunehisa Sakoda

High-Performance and Low-Power Bulk Logic Platform Utilizing FET Specific Multiple-Stressors with Highly Enhanced Strain and Full-Porous Low-k Interconnects for 45-nm CMOS Technology

We present an aggressively-scaled high-performance and low-power bulk CMOS platform technology aiming at large-scale (multi-core) high-end use with 45-nm ground rule. By utilizing a high-epsilon offset spacer and FET specific multiple-stressors with highly enhanced strain, world competitive high performance NFET and PFET drive currents of 1.22/0.765 mA/mum at 100 nA/mum off-current, and 0.97/0.63 mA/mum at 10 nA/mum off-current at |Vd|= 1V, respectively, were obtained with minimizing layout dependence. This technology also offers a functional high density SRAM with a much smaller cell, i.e., 0.255 mum2. In addition, full- porous low-k (k = 2.25) BEOL integration lowers RC delay and reduces total circuit delay by 25% at the long wiring region compared to that of our previous technology.

Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an Ioff = 9 [nA/mum] for PMOS / NMOS). We also demonstrate that the fluorine co-implant plays a large role in reducing the PMOS source-drain extension (SDE) resistance.

Formation of HfSiON/SiO/sub 2//Si-substrate gate stack with low leakage current for high-performance high-/spl kappa/ MISFETs

The authors found the method to form HfSiON film with an ultrathin SiO/sub 2/ interfacial layer on the Si substrate by oxidizing the HfSiN. The HfSiN film was deposited by using the metal-organic chemical vapor deposition reactor with the shower head, supplying metal (Hf and Si) precursors and NH/sub 3/ gas separately from discharge nozzles. The authors successfully decreased the leakage current of the metal insulator semiconductor diode with HfSiON/SiO/sub 2/ insulator of 1-nm equivalent oxide thickness to 0.036 A/cm/sup 2/ at V/sub fb/-1 V.

High-Performance Low Operation Power Transistor for 45nm Node Universal Applications

High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Youngs modulus (YM) offset spacer covered with dual stress liner (DSL), were used for electron and hole mobility enhancement and parasitic resistance (Rsd) reduction. The junction profile was also carefully optimized for low leakage current. As a result of a 12% mobility improvement and a 30% Rsd reduction, enhancements of 19 and 14% and Ion(@Ioff= 5 nA/mum) of 620 and 830 muA/mum were achieved for NMOS at 0.85 and 1.0V, respectively. As a result of a 45% mobility improvement and a 25% Rsd reduction, the enhancements of 32 and 22% and Ion of 330 and 440 muA/mum were achieved for PMOS at 0.85 and 1.0V, respectively. These results are the best Ion-Ioff tradeoff characteristics among the recent LOP transistors

1st quantitative failure-rate calculation for the actual large-scale SRAM using ultra-thin gate-dielectric with measured probability of the gate-current fluctuation and simulated circuit failure-rate

We investigated the influence over intermittent SRAM failure by gate current, Ig, fluctuation for the first time. In this paper, we also describe the difference of SRAM failure due to Ig fluctuations between MOS transistors before and after stressing. We have quantitatively confirmed that Ig fluctuation causes SRAM failure.

Ti-capping technique as a breakthrough for achieving low threshold voltage, high mobility, and high reliability of pMOSFET with metal gate and high-k dielectrics technologies

We have proposed inhibition mechanism of common Al-capping technique for pMOSFET threshold-voltage (Vth) control for the first time, and have established effective Ti-capping technique using metal gate and Hf-based high-k dielectrics. Ti-capping technique can adjust lower Vth than Al-capping one due to the suppression of counter dipole and solid solubility limit in doping. Moreover, Ti-capping technique can improve carrier mobility and negative bias temperature instability (NBTI). We have confirmed that Ti-doped devices achieve higher performance, and the technique is suitable for 32 nm-technology node and beyond.

Layout optimization to maximize tolerance in SEILA: Soft error immune latch

The purpose of this paper is optimization of layout on soft error immune latch (SEILA) for maximizing soft-error mitigation efficiency, and investigating mechanisms of charge collection on multi-node and discussing layout dependence on soft-error. We evaluate soft-error rate (SER) on un-robust latch, conventional robust latch, SEILA with changing well structure, distances from well-contacts, and distance between soft-error critical nodes through neutron acceleration experiments at Osaka Univ. Soft-error mitigation efficiency awfully change with changing layout. In designing robust latches, it is most important for high the mitigation to separated critical nodes with STI and we need to take care on layout especially distance between critical nodes.

Advanced BEOL integration using porous low-k (k=2.25) material with charge damage-less electron beam cure technique

As a practical curing technique of low-k material for 32-nm BEOL technology node, we demonstrated that electron beam (e-beam) irradiation was effective to improve film properties of nano-clustering silica (NCS). We confirmed that by using optimized e-beam cure condition, NCS was successfully hardened without degradation of dielectric constant and the Youngs modulus increased by 1.7 times compared with that of thermally cured NCS. We fabricated two-level Cu wirings layers with NCS cured by optimized e-beam cure technique. The e-beam cure dramatically enhanced the lifetime of time-dependent dielectric breakdown (TDDB) of interlayer dielectrics. We also examined the influence of the charge damage to the MOSFETs under e-beam cured NCS layer and confirmed that there was no e-beam charge damage to the Ion-Ioff characteristics and reliability of MOSFETs with the optimized e-beam cure.

Cost-effective Ni-melt-FUSI boosting 32-nm node LSTP transistors

We demonstrated for the first time that novel Ni-FUSI process using FLA (Melt-FUSI) dramatically improved both electrical characteristics and cost-benefit performance of LSTP devices. Since the T_inv was aggressively scaled (T_inv = 2.1 nm) with keeping SiON-gate leakage current and increasing hole mobility twice, we achieved the record I_on of 300 muA/mum at the I_off of 20 pA/mum for the pMOS transistor with the L_g of 45 nm at V_d of -1.2 V.

Characterization of millisecond-anneal-induced defects in SiON and SiON/Si interface by gate current fluctuation measurement

In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of MOSFET.