Yuui Shimizu

Random telegraph noise in flash memories - model and technology scaling

This paper presents the first statistical model of Vt fluctuation (ΔVt_cell) in a floating-gate flash memory due to random telegraph noise. It considers current-path percolation, which generates a large-amplitude-noise tail, caused by dopant induced surface potential non-uniformity It concludes that the impact of scaling is weaker than the widely-accepted 1/L_effW_eff trend. 3-σ ΔVt_cell is estimated to increase by 1.8x rather than ≫10x from 90 nm to 20 nm technology nodes.

A 19 nm 112.8 mm

NAND flash memory is widely used in digital cameras, USB devices, cell phones, camcorders and solid-state drives. Continuous lowering of bit cost, increasing flash-memory-die densities and improving performance have helped to expand flash markets. Recently, there are two different directions to meet market demands. One is lowering bit cost and increase memory density to the utmost limit, which is achieved by 4b/cell [1] or 3b/cell [2]. The other is focusing on high performance and high reliability. To meet both demands, we develop a 19nm 112.8mm2 64Gb 2b/cell NAND flash memory with the smallest die size ever reported. 15MB/s programming throughput and 400Mb/s/pin 1.8V Toggle Mode interface [3] are achieved for the first time. Die Micrograph and features are shown in Figure 25.1.1.

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A 16Mb MRAM based on 0.13mum CMOS and 0.24mum MRAM process achieves a 34ns asynchronous access and 100MHz synchronous operation, compatible with pseudo-SRAM for mobile applications. By implementation of FORK wiring scheme, the cell efficiency is raised to 39.9% and the disturb robustness of half-selection state is improved

64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

The writing region and the repeatability of the function test and switching current fluctuation of magnetoresistive random access memory (MRAM) with a propeller shape magnetic tunnel junction (MTJ) array is evaluated. The effect of the write sequence is also investigated. The writing region is larger when the easy-axis field pulse is turned on prior to the hard-axis field than that in the case of the opposite sequence. However, the total margin in the latter sequence is larger after the repeated tests because of the smaller switching field fluctuation. The average 1-sigma value of the switching field fluctuation is 1.7%, which is mainly caused by the thermal fluctuation. The probability of the write error is estimated to be less than 10-16 by the bit line writing region and the thermal stability

A 16Mb MRAM with FORK Wiring Scheme and Burst Modes

Technologies for realizing high density MRAM were developed. First, new circuitry to lower the resistance of programming wires was developed. Second, both MTJ plane shape and cross-sectional structure were optimized to lower the programming current. Based on these two technologies, 16 Mb MRAM was designed, fabricated with 130 nm CMOS process and 240 nm back end MTJ process. As a result, a 1.8 V power supply MRAM with 42.3% array efficiency was successfully demonstrated

Switching Current Fluctuation and Repeatability for MRAM With Propeller-Shape MTJ

A new test pattern, quadruplet checker board (QCKBD), is proposed which enables to evaluate magnetic crosstalk from the neighbor write lines. At first, some conventional test patterns changing the write points were applied to categorize magnetic random access memory (MRAM) write errors. But magnetic crosstalk from the neighbor write lines could not be isolated by these conventional tests since magnetic crosstalk error was caused when the neighbor cell is written. Whereas the QCKBD results from 4Kb test vehicles show that magnetic crosstalk restricts the write margin. By changing the cell structure in order to suppress magnetic crosstalk, the write margin is improved from 3.3 to 7.3

1.8 V Power Supply 16 Mb-MRAMs With 42.3% Array Efficiency

In this paper, we investigate the thermal energy of MRAM cells on applied field along the easy or hard axis and its dependence on magnetic domain pattern. Furthermore the thermal stability at half-selected situation is also discussed.