Zhen-Ying Hsieh

Visible Light Source Disturbing the Source/Drain Current of CLC Poly-Si n-TFT Device

CLC Poly-Si n-TFT Device M.C. Wang, Z.Y. Hsieh, C. Chen, J.M. Shieh, Y.T. Lin, H.S. Huang Institute of Mechatronic Engineering, National Taipei University of Technology, Taipei, 10601, Taiwan Department of Material Science & Engineering, National Chiao Tung University, Hsinchu 300, Taiwan National Nano Device Laboratories, Hsinchu 30078, Taiwan *Dept. of Electronic Engineering, Ming-Hsin University of Science and Technology; No. 1 Hsin-Hsing Road, Hsin-Fong, Hsin-Chu, 304, Taiwan; e-mail: mucwang@must.edu.tw.

Efficiency analysis of electroplating gold bump in assembly

In flat panel displays, the assembly format of driving ICs, due to the rectangular chip shape, is usually with a difference of conventional commercial ICs constructed with a square configuration. Because of this concern, the electroplating gold bump technology in package was desirably developed. Additionally, in the characteristics of hardness, melting point, and stability, gold material is generally better than tin material. Although tin in cost is lower than gold, the previous just can be applied to the soldering joint, but not to the thermal compression process. Therefore, in this study, the electroplating gold bump in assembly was probed in detail to analyze the possibility of mass-production.

Dual fiber-optic Fabry-Perot interferometer temperature sensor with low-cost light-emitting diode light source

A dual fiber-optic Fabry–Perot interferometer (FFPI) sensor system with a low-coherence communication-system light-emitting diode (LED) as a light source is investigated to detect temperature variation signals. In this system, there are two FFPIs: the sensing and reference FFPIs. When the perturbation of interest, such as that of temperature, disturbs the sensing FFPI to produce a phase shift, the light reflected from the sensor is demodulated by the reference FFPI to extract the measurand. A low-power (sub-nW) optical signal is converted into an electrical signal and processed by a designed optical receiver. This setup is availably applied in biosensors to compensate the temperature variation in a sensing environment or sense the temperature effect in a certain measurement on an interior local site.

An efficient metrology to sense micro-metal contamination in fine-pitch package

In the infant mortality (IM) experiment and the final test (FT) of IC reliability, the screening capability for the contaminated metal particles is generally over than the size, W × L ∼ 120 × 120 um2. For the smaller size of these metal particles in ICs, the IM test is inferior. Using an efficient test metrology combining the IM test and the soak test to stress the sampled SRAM (Static random access memory) ICs, the smaller contaminated metal size with scanning electron microscope was measured, about W × L = 15 × 120 um2. The composition of metal particle with energy-dispersive X-ray (EDX) in material analysis exhibited two main peaks attributed to manganese (Mn) and ferrum (Fe). In speculation, the humidity effect after the soak test provided the electro-chemical reaction environment between two neighboring IC pins, spacing 130 um, in the fine pitch package. The IM test enhancing the electrical field accelerated this electro-chemical reaction. Therefore, even though the smaller contaminated metal particles exist, they with the double-combination test still can be screened out. Due to this effort, the risk selling ICs to customers is tremendously reduced. The assembly houses after information feedback are able to trace the root causes in production line and improve the package yield.

A 2.4-GHz 0.18μm Full-CMOS Single-Stage Class-E Power Amplifier With Temperature Effect for ISM Band Wireless Communication

In this paper, we present a single-stage class-E power amplifier with multiple-gated shape as well as 0.18μm complementary metal-oxide-semiconductor (CMOS) process for 2.4GHz Industry-Science-Medicine (ISM) band. This power amplifier is able to be easily integrated into the system-on-chip (SoC) circuit. For the competition of lower cost and high integration in marketing concern, CMOS technology is fundamentally better than GaAs technology. We adopt the Advanced Design System software in circuit simulation coming from Agilent Company through the Chip Implementation Center (CIC) channel plus TSMC 0.18 μm device models. The simulation results with temperature effect, show the good performance such as an output power achievement of +22dBm under a 1.8V supply voltage; the power-added efficiency (PAE) is over 30%; the output impedance (S22 ) and the input impedance (S11 ) are fully lower than −15dB; the power gain (S21 ) is +11dB; the inverse isolation (S12 ) is below −26dB. This amplifier reaches its 1-dB compression point at an output level of 16.5dBm related to the input power 6.5dBm position. The output power with temperature variation from 0°C to 125°C depicts an acceptable spec. range, too.© 2007 ASME

Influence of plastic assembly yield with molding technology

The molding technology in IC assembly is to protect the ICs avoiding the external damage and indirectly provide the heat dissipation. The molding pattern design, transfer-mold system, providing the drawing pipeline for liquid molding compound in molding is not only the technical index, but the key in the assembly throughput. Furthermore, the integrity of molding compound in plastic assembly is the main role of assembly quality. Analyzing these two factors impacting the assembly performance is the chief investigation in this work.

A study to stencil printing technology for solder bump assembly

In general, the stencil printing manufacturing in pre-WLCSP (wafer-level chip-scale packaging) is able to be integrated by 7-step processes, including two masks and one set of stencil plate. After the formation of solder ball, the specified professional probe card is needed to verify whether the electric functions of this packaged IC are good. After this step, the wafer grinding, the wafer cutting, the chip choice and the final test (F/T) are gradually adopted to proceed. Finally, due to the customers need, the shipping package type to customers is, generally, tray or tape and reel. Although the stencil printing technology can provide the mass-production capability, the mainly existing problems of this technology are the quality of manufacturing steel plate, the coating operation for solder paste, and the flatness of wafer surface. These issues usually constrain the minimization of the size of the solder ball and the pitch. Thinking to solve these issues, this package technology is still feasible in assembly competition.

Trend transformation of drain-current degradation under drain-avalanche hot-carrier stress for CLC n-TFTs

Continuous-wave green laser-crystallized (CLC) single-grain-like polycrystalline silicon n-channel thinfilm transistors (poly-Si n-TFTs) demonstrate the higher electron mobility and turn-on current than excimer laser annealing (ELA) poly-Si n-TFTs. Furthermore, high drain voltage accelerates the flowing electrons in n-type channel, and hence the hot-carriers possibly cause a serious damage near the drain region and deteriorate the source/drain (S/D) current. In this study, at high drain stress voltage, it appears that CLC TFT was degraded in the initial stress time (before 50 s), but the drain current was enhanced after 50 s. After 50 s stress time, the amount of grain boundary trap states near the drain side was getting large and the reflowing holes damaged the source region or injected into gate oxide near source side as well.

Gate-to-drain capacitance verifying the continuous-wave green laser crystallization n-TFT trapped charges distribution under dc voltage stress

In this work, a metrology was proposed to realize the distribution of fixed oxide trapped charges and grain boundary trapped states. The (continuous-wave green laser crystallization) n-channel thin-film transistors (TFTs) were forced by dc voltage stress, VG=VD. The gate-to-drain capacitance, CGD−VG, with varying frequency of applied small signal was developed. To probe the distribution of these defects, the difference (initial capacitance values minus stressed capacitance values) of CGD−VG with different frequencies was precisely studied.

Effective Edge Width for 65-nm pMOSFETs and Their Variations Under CHC Stress

The narrow-width <i>W</i> effect of metal-oxide-semiconductor field-effect transistors (MOSFETs) with shallow trench isolation technology has been widely reported. The factor of most concern is the edge width Δ<i>w</i> affecting the electrical characteristics of the MOSFETs. In this letter, the negative variation value of Δ<i>w</i>, as explained in the content, was derived from 65-nm node p-channel MOSFETs (pMOSFETs). To verify the validity of Δ<i>w</i>, the pMOSFETs were stressed by channel-hot-carrier stress conditions. According to the experimental results, the device parameter degradation, i.e., the threshold voltage <i>V</i>_TH, was obviously dominated by |Δ<i>w</i>|/W, and the degradation of the narrow-width device was also increased for the wide width.