Zhixian Chen

Vertical Si-Nanowire

This letter presents a Si nanowire based tunneling field-effect transistor (TFET) using a CMOS-compatible vertical gate-all-around structure. By minimizing the thermal budget with low-temperature dopant-segregated silicidation for the source-side dopant activation, excellent TFET characteristics were obtained. We have demonstrated for the first time the lowest ever reported subthreshold swing (SS) of 30 mV/decade at room temperature. In addition, we reported a very convincing SS of 50 mV/decade for close to three decades of drain current. Moreover, our TFET device exhibits excellent characteristics without ambipolar behavior and with high Ion/Ioff ratio (105), as well as low Drain-Induced Barrier Lowering of 70 mV/V.

n

We present a vertical-silicon-nanowire-based p-type tunneling field-effect transistor (TFET) using CMOS-compatible process flow. Following our recently reported n-TFET , a low-temperature dopant segregation technique was employed on the source side to achieve steep dopant gradient, leading to excellent tunneling performance. The fabricated p-TFET devices demonstrate a subthreshold swing (SS) of 30 mV/decade averaged over a decade of drain current and an Ion/Ioff ratio of >; 105. Moreover, an SS of 50 mV/decade is maintained for three orders of drain current. This demonstration completes the complementary pair of TFETs to implement CMOS-like circuits.

-Type Tunneling FETs With Low Subthreshold Swing (

For the first time, nano-meter-scaled 1T-1R non-volatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated. Transistors are fabricated using fully CMOS compatible technology and RRAM cells are stacked onto the tip of the nano-pillars (with a diameter down to ~37nm) to achieve a compact 4F2 footprint. In addition, through this platform, different RRAM stacks comprising CMOS friendly materials are studied, and it is found that TiN/Ni/HfO2/n+-Si RRAM cells show excellent switching properties in either bipolar or unipolar mode, including (1) ultra-low switching current/power: SET ~20nA/85nW and RESET ~200pA/700pW, (2) multi-level switchability, (3) good endurance, >105, (4) satisfactory retention, 10 years at 85oC; and (5) fast switching speed ~50ns. Moreover, this vertical (gate-all-around) GAA nano-pillar based 1T-1R architecture provides a more direct and flexible test vehicle to verify the scalability and functionality of RRAM candidates with a dimension close to actual application.

\leq \hbox{50}\ \hbox{mV/decade}

Smooth N-polar InGaN/GaN and AlGaN/GaN multiquantum wells (MQWs) and heterostructures were grown by metal organic chemical vapor deposition on (0001) sapphire substrates with misorientation angles of 2°–5° toward the a-sapphire plane. For all investigated structures the tendency toward formation of multiatomic steps at the film surface and at interfaces increased with increasing misorientation angle. Thereby the crystal misorientation led to a stronger degradation of the interface quality and periodicity of InGaN/GaN in comparison to the AlGaN/GaN MQWs. While the alloy composition of AlGaN films was unaffected by the misorientation, the indium mole fraction in the InGaN layers and the wavelength of the MQW related luminescence decreased with increasing misorientation angle. The properties of the two dimensional electron gas (2DEG), which formed at the upper interface of semi-insulating GaN/AlGaN/GaN heterostructures, were strongly anisotropic. Whereas the resistivity of the 2DEG measured perpendicular to ...

) at Room Temperature

This paper reviews the progress of the vertical top-down nanowire technology platform developed to explore novel device architectures and integration schemes for green electronics and clean energy applications. Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. Under clean energy harvesting area, vertical wires could provide (1) cost reduction in photovoltaic energy conversion through enhanced light trapping and (2) a fully CMOS compatible thermoelectric engine converting waste-heat into electricity. In addition to progress review, we discuss the challenges and future prospects with vertical nanowires platform.

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high ION/IOFF ratio (>; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

\leq 50

In this letter, we report for the first time the degradation mechanism of drain current in tunneling field-effect transistors (TFETs). Using positive-bias and hot-carrier (HC) stress experiments and TCAD simulation, we show that the drain current degradation is mainly induced by the interface traps and/or oxide charge located above the tunneling region, causing reduction of tunneling field and tunneling current. The interface traps mainly induce the degradation in transconductance, while the oxide charge essentially causes a threshold-voltage shift in TFETs. The results show that the interface-trap generation is dominant under a positive-bias stress, while the oxide-charge creation is important under an HC stress in n-TFETs.

-mV/decade Subthreshold Swing

A fully CMOS-compatible vertical nanopillar gate-all-around transistor integrated with a transition-oxide-based resistive random access memory cell to realize 4F2 footprint has been demonstrated and systematically characterized. The nanopillar transistor exhibits excellent transfer characteristics with diameter scaled down to a few tens of nanometer. Three types of resistive switching behavior have been observed in the fabricated one-transistor one-resistor cell, namely, preforming ultralow-current switching, unipolar switching, and bipolar switching after forming process. A reset current of only 200 pA has been observed in the preforming ultralow-current switching, while for the unipolar and bipolar switching modes after forming process, good memory performance and operation parameter uniformity are demonstrated. Furthermore, reset current is found to decrease with reducing nanopillar transistor design diameter, which is beneficial for circuit power consumption consideration.

Highly compact 1T-1R architecture (4F 2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation

AlGaN/GaN high-electron mobility transistors with different Al compositions and barrier thicknesses were compared. The samples with higher Al composition and similar 2D electron gas density showed higher gate leakage, utilizing a slant field plate gate process. By applying a gate recess etch and a slant field plate gate process, gate leakage was improved to a similar level for all the devices, and the power density and PAE were much improved.

Influence of the substrate misorientation on the properties of N-polar InGaN/GaN and AlGaN/GaN heterostructures

For the first time, we demonstrate the fabrication of two independently controlled gate-all-around MOSFETs on a single vertical silicon nanowire using CMOS process technology. The second gate is vertically stacked on top of the first gate without occupying additional area and thereby achieving true 3-D integration. The fabricated devices exhibit very low leakage, tunability in drain current, as well as “AND” gate functionality with 50% reduction in area for both n- and p-type MOSFETs. The twin-gate device structure is also promising for implementing other device types such as stacked SONOS memory and tunneling FET. We anticipate that our vertically integrated device architecture will provide unique opportunities for realizing ultra-dense CMOS logic on a single nanowire.