X. P. Wang

Highly compact 1T-1R architecture (4F 2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation

For the first time, nano-meter-scaled 1T-1R non-volatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated. Transistors are fabricated using fully CMOS compatible technology and RRAM cells are stacked onto the tip of the nano-pillars (with a diameter down to ~37nm) to achieve a compact 4F2 footprint. In addition, through this platform, different RRAM stacks comprising CMOS friendly materials are studied, and it is found that TiN/Ni/HfO2/n+-Si RRAM cells show excellent switching properties in either bipolar or unipolar mode, including (1) ultra-low switching current/power: SET ~20nA/85nW and RESET ~200pA/700pW, (2) multi-level switchability, (3) good endurance, >105, (4) satisfactory retention, 10 years at 85oC; and (5) fast switching speed ~50ns. Moreover, this vertical (gate-all-around) GAA nano-pillar based 1T-1R architecture provides a more direct and flexible test vehicle to verify the scalability and functionality of RRAM candidates with a dimension close to actual application.

Analytic model of endurance degradation and its practical applications for operation scheme optimization in metal oxide based RRAM

An analytic model for the endurance degradation of metal oxide based RRAM is presented for the first time. The endurance degradation behaviors under various operation modes can be predicted by the model, which were verified by the measured data in different devices. Furthermore, the 106 endurance for all 4-level resistance states in HfOX-based RRAM is demonstrated by using the proposed optimization operation scheme for multi-level data storage based on the model prediction. Guided by the model, a dynamic self-recovery operation scheme is developed to achieve more than 2 orders endurance enhancement at a high switching speed (10 ns).

Fully CMOS-Compatible 1T1R Integration of Vertical Nanopillar GAA Transistor and Oxide-Based RRAM Cell for High-Density Nonvolatile Memory Application

A fully CMOS-compatible vertical nanopillar gate-all-around transistor integrated with a transition-oxide-based resistive random access memory cell to realize 4F2 footprint has been demonstrated and systematically characterized. The nanopillar transistor exhibits excellent transfer characteristics with diameter scaled down to a few tens of nanometer. Three types of resistive switching behavior have been observed in the fabricated one-transistor one-resistor cell, namely, preforming ultralow-current switching, unipolar switching, and bipolar switching after forming process. A reset current of only 200 pA has been observed in the preforming ultralow-current switching, while for the unipolar and bipolar switching modes after forming process, good memory performance and operation parameter uniformity are demonstrated. Furthermore, reset current is found to decrease with reducing nanopillar transistor design diameter, which is beneficial for circuit power consumption consideration.

Current Conduction Model for Oxide-Based Resistive Random Access Memory Verified by Low-Frequency Noise Analysis

A conduction model consisting of two parallel resistances from a highly conductive filament region and a uniform leakage oxide region is proposed in this brief to represent the current conduction in the filament-type switching resistive random access memory cell. Low-frequency noise analysis of current fluctuation at different resistance states has been employed to verify its efficiency. It is found that, in the low-resistance regime, filament resistance dominates current conduction and noise varies as a power law of resistance, whereas in the high-resistance regime, uniform oxide leakage is the major source of conduction, giving rise to a nearly constant noise level.

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.

Impact of Ni Concentration on the Performance of Ni Silicide/HfO2/TiN Resistive RAM (RRAM) Cells

We present a study of Ni silicide as the bottom electrode in HfO2-based resistive random-access memory cells. Various silicidation conditions were used for each device, yielding different Ni concentrations within the electrode. A higher concentration of Ni in the bottom electrode was found to cause a parasitic SET operation during certain RESET operation cycles, being attributed to field-assisted Ni cation migration creating a Ni filament. As such, the RESET is affected unless an appropriate RESET voltage is used. Bottom electrodes with lower concentrations of Ni were able to switch at ultralow currents (RESET current <1 nA) by using a low compliance current (<500 nA). The low current is attributed to the tunneling barrier formed by the native SiO2 at the Ni silicide/HfO2 interface.

Study of Multilevel High-Resistance States in HfO x -Based Resistive Switching Random Access Memory by Impedance Spectroscopy

Multilevel high-resistance states are achieved in TiN/HfOx/Pt resistive switching random access memory device by controlling the reset stop voltage. Impedance spectroscopy is used to study the multilevel high-resistance states. It is shown that the high-resistance states can be described with an equivalent circuit consisting of the major components Rs, R, and C corresponding to the series resistance of the TiON interfacial layer, the equivalent parallel resistance, and capacitance of the leakage gap between the TiON layer and the residual conductive filament, respectively. These components show a strong dependence on the stop voltage, which can be explained in the framework of oxygen vacancy model and conductive filament concept. On the other hand, R is observed to decrease with dc bias, which can be attributed to the barrier lowering effect of the Coulombic trap well in the Poole-Frenkel emission model.

Fully CMOS compatible 1T1R integration of vertical nanopillar GAA transistor and Oxide based RRAM cell for high density nonvolatile memory application

Fully CMOS compatible vertical nanopillar GAA transistor integrated with Oxide based RRAM cell to realize 4F2 footprint has been demonstrated and systematically characterized. Nanopillar transistor exhibits excellent transfer characteristics with diameter down to a few tens nanometer. Three type of resistive switching behavior have been found in the fabricated 1T1R cell, namely pre-forming ultralow current switching, unipolar switching and bipolar switching after forming process. Reset current of only 200pA has been observed in pre-forming ultralow current switching; while for unipolar and bipolar switching after forming process, good memory performance and operation parameter uniformity is demonstrated. Furthermore, reset current is found to decrease with reducing nanopillar transistor design diameter, which is beneficial for circuit power consumption concern.

Ni-Containing Electrodes for Compact Integration of Resistive Random Access Memory With CMOS

Different HfOx-based resistive random access memory stacks with Ni-containing electrodes, including NiSi and Ni(Ge1-xSix), which can be easily formed on the source/drain of a transistor, are systematically investigated in this letter. The involvement of Ni (or NiOx formed) at the interface has been found very beneficial to good switching properties. Moreover, RESET current can be effectively reduced for silicide electrodes compared to the n+ -Si case, attributed to the formation of a thicker interfacial layer involving NiOx and/or GeOx. In addition, a well-controlled interfacial layer is believed to be very helpful for the switching uniformity improvement. All these observations suggest the prospect of a compact 1T-1R integration scheme with Ni-containing electrodes.

Area Dependent Low Frequency Noise in Metal Oxide Based Resistive Random Access Memory

Metal oxide based resistance random access memory (RRAM) has been extensively studied as one of the most promising candidate for next generation nonvolatile memory; however the current conduction mechanism is not yet clearly understood. To tackle this problem, low frequency noise behavior in metal oxide based RRAM device has been investigated in this work. Together with DC current voltage characteristics, it confirms that for the low resistance state, current conduction is localized without an area dependence, whereas, for the high resistance state, it is a uniform leakage current throughout the whole device area. This is consistent with the filament type resistive switching phenomenon in such devices.