Aashit Kamath

Highly compact 1T-1R architecture (4F 2 footprint) involving fully CMOS compatible vertical GAA nano-pillar transistors and oxide-based RRAM cells exhibiting excellent NVM properties and ultra-low power operation

For the first time, nano-meter-scaled 1T-1R non-volatile memory (NVM) architecture comprising of RRAM cells built on vertical GAA nano-pillar transistors, either junction-less or junction-based, is systematically investigated. Transistors are fabricated using fully CMOS compatible technology and RRAM cells are stacked onto the tip of the nano-pillars (with a diameter down to ~37nm) to achieve a compact 4F2 footprint. In addition, through this platform, different RRAM stacks comprising CMOS friendly materials are studied, and it is found that TiN/Ni/HfO2/n+-Si RRAM cells show excellent switching properties in either bipolar or unipolar mode, including (1) ultra-low switching current/power: SET ~20nA/85nW and RESET ~200pA/700pW, (2) multi-level switchability, (3) good endurance, >105, (4) satisfactory retention, 10 years at 85oC; and (5) fast switching speed ~50ns. Moreover, this vertical (gate-all-around) GAA nano-pillar based 1T-1R architecture provides a more direct and flexible test vehicle to verify the scalability and functionality of RRAM candidates with a dimension close to actual application.

Realizing and and or Functions With Single Vertical-Slit Field-Effect Transistor

This letter experimentally demonstrates and and or functionalities with a single MOS transistor. Device architecture and fabrication follow the recent work on fabrication-based feasibility assessment of junctionless vertical-slit field-effect transistor. Slit width variation is used to realize a particular functionality-wider for or function and narrower for and function. The fabricated n-type devices with the and and or functionalities exhibit good electrical performance: low off current (<; 5 pA/μm) and high ION/IOFF ratio (>; 106). Furthermore, we briefly discuss the implication of these devices in CMOS NAND logic implementation.

Fully CMOS-Compatible 1T1R Integration of Vertical Nanopillar GAA Transistor and Oxide-Based RRAM Cell for High-Density Nonvolatile Memory Application

A fully CMOS-compatible vertical nanopillar gate-all-around transistor integrated with a transition-oxide-based resistive random access memory cell to realize 4F2 footprint has been demonstrated and systematically characterized. The nanopillar transistor exhibits excellent transfer characteristics with diameter scaled down to a few tens of nanometer. Three types of resistive switching behavior have been observed in the fabricated one-transistor one-resistor cell, namely, preforming ultralow-current switching, unipolar switching, and bipolar switching after forming process. A reset current of only 200 pA has been observed in the preforming ultralow-current switching, while for the unipolar and bipolar switching modes after forming process, good memory performance and operation parameter uniformity are demonstrated. Furthermore, reset current is found to decrease with reducing nanopillar transistor design diameter, which is beneficial for circuit power consumption consideration.

Impact of Ni Concentration on the Performance of Ni Silicide/HfO2/TiN Resistive RAM (RRAM) Cells

We present a study of Ni silicide as the bottom electrode in HfO2-based resistive random-access memory cells. Various silicidation conditions were used for each device, yielding different Ni concentrations within the electrode. A higher concentration of Ni in the bottom electrode was found to cause a parasitic SET operation during certain RESET operation cycles, being attributed to field-assisted Ni cation migration creating a Ni filament. As such, the RESET is affected unless an appropriate RESET voltage is used. Bottom electrodes with lower concentrations of Ni were able to switch at ultralow currents (RESET current <1 nA) by using a low compliance current (<500 nA). The low current is attributed to the tunneling barrier formed by the native SiO2 at the Ni silicide/HfO2 interface.

Fully CMOS compatible 1T1R integration of vertical nanopillar GAA transistor and Oxide based RRAM cell for high density nonvolatile memory application

Fully CMOS compatible vertical nanopillar GAA transistor integrated with Oxide based RRAM cell to realize 4F2 footprint has been demonstrated and systematically characterized. Nanopillar transistor exhibits excellent transfer characteristics with diameter down to a few tens nanometer. Three type of resistive switching behavior have been found in the fabricated 1T1R cell, namely pre-forming ultralow current switching, unipolar switching and bipolar switching after forming process. Reset current of only 200pA has been observed in pre-forming ultralow current switching; while for unipolar and bipolar switching after forming process, good memory performance and operation parameter uniformity is demonstrated. Furthermore, reset current is found to decrease with reducing nanopillar transistor design diameter, which is beneficial for circuit power consumption concern.

Ni-Containing Electrodes for Compact Integration of Resistive Random Access Memory With CMOS

Different HfOx-based resistive random access memory stacks with Ni-containing electrodes, including NiSi and Ni(Ge1-xSix), which can be easily formed on the source/drain of a transistor, are systematically investigated in this letter. The involvement of Ni (or NiOx formed) at the interface has been found very beneficial to good switching properties. Moreover, RESET current can be effectively reduced for silicide electrodes compared to the n+ -Si case, attributed to the formation of a thicker interfacial layer involving NiOx and/or GeOx. In addition, a well-controlled interfacial layer is believed to be very helpful for the switching uniformity improvement. All these observations suggest the prospect of a compact 1T-1R integration scheme with Ni-containing electrodes.