I. Debusschere

Highly Scaled Vertical Cylindrical SONOS Cell With Bilayer Polysilicon Channel for 3-D nand Flash Memory

A vertical cylindrical SONOS cell with a novel bilayer polysilicon channel down to 22-nm diameter for 3-D NAND Flash memory is successfully developed. We introduce a thin amorphous silicon layer along with the oxide-nitride-oxide (ONO) gate stack inside the memory hole. This silicon layer protects the tunnel oxide during opening of the gate stack at the bottom of the memory hole, after which it serves as the first layer of the bilayer polysilicon channel. This approach enables the 3-D architecture to achieve minimum cell area (4F2, with F being the feature size) without the need for the so-called pipeline connections. The smallest functional cells have the memory hole diameter F = 45 nm, resulting in 22-nm channel diameter. In case 16 cells are stacked, F = 45 nm would correspond to an equivalent 11-nm planar cell technology node. Excellent program/erase and retention obtained with the all-deposited ONO stack are demonstrated.

Hybrid Floating Gate Cell for Sub-20-nm NAND Flash Memory Technology

The hybrid floating gate (FG) concept, previously demonstrated in FG capacitors, has been proven in fully integrated stacked memory cells. Results not only confirm the high potential of the concept in terms of improved program performance, but also show excellent data retention and program/erase cycling endurance. Key for achieving this result has been the optimization of the sidewall and spacer processing. Hybrid FG cells are therefore a viable solution to extend the nand Flash memory roadmap below the 20-nm technology node.

Integration of CMOS-electronics and particle detector diodes in high-resistivity silicon-on-insulator wafers

A new approach to monolithic pixel detectors, based on silicon on insulator (SOI) wafers with high resistivity substrate, is being pursued by the CERN RD19 collaboration. The fabrication methods and the results of the electrical evaluation of the SOI-MOSFET devices and of the detector structures fabricated in the bulk are reported. The leakage current of the high-resistivity PIN-diodes is kept of the order of 5 to 10 nA/cm/sup 2/. The SOI preparation processes employed-SIMOX (separation by implantation of oxygen) and ZMR (zone melting recrystallization)-produce working electronic circuits, and appear to be compatible with the fabrication of detectors of suitable quality. >

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

Novel dual layer floating gate structure as enabler of fully planar flash memory

Flash pitch scaling will lead to cells for which the wordline no longer fits between the floating gates, which results in loss of sidewall coupling, causing unacceptable program saturation due to IPD leakage. We present a dual layer poly/metal floating gate (FG) memory device avoiding this saturation and demonstrate +4V programming above the fresh level in a fully planar cell without sidewall coupling using an Al2O3 IPD. The data retention at 200C and cycling performance up to 100k cycles are similar to cells with poly FG.

An Ultra-Thin Hybrid Floating Gate Concept for Sub-20nm NAND Flash Technologies

A nonvolatile memory structure with hybrid (poly/metal) floating gate in combination with an Al2O3 interpoly dielectric is investigated for sub-20nm scaling. Floating gate thickness scaling down to only 5nm with excellent program/erase performance and reliability is demonstrated to address the issue of increased cell-to-cell interference. It is further shown that a hybrid floating gate also offers great benefit when used in combination with ONO, which still is the conventional interpoly dielectric layer used in state-of-the-art floating gate Flash memories.

Thin L-shaped spacers for CMOS devices

This work presents the use of ultimately thin (15 nm) L-shaped spacers to open the process window for deposition-related steps. Whereas conventional spacers prevent the correct active area silicidation between two closely located transistors, these thin L-shaped spacers allow the formation of a low resistive active interconnect between transistors as close as 40 nm apart. With respect to conventional spacers, thin L-shaped spacers show equally good silicide bridging immunity, device characteristics and electrostatic discharge performance.

Standard cell level parasitics assessment in 20nm BPL and 14nm BFF

It is shown that the performance impact of middle-of-line (MOL) patterning process variations can be reduced by 30% by relaxing the standard cell gate pitch by 10% in both 20nm bulk planar (BPL) and 14nm bulk finFET (BFF). Tungsten can safely replace copper in local interconnect IM2, which allows the MOL critical dimensions (CD) to be reduced by 40% in 20nm BPL, resulting in 5% performance improvement. In 14nm BFF, 10% performance degradation can be traded in for 40% smaller IM1 contact area, allowing for a cell silicon footprint benefit of up to 20%.

Ultra thin hybrid floating gate and high-k dielectric as IGD enabler of highly scaled planar NAND flash technology

For the first time we demonstrate ultra-thin hybrid floating gate (HFG) planar NVM cell performance and reliability. Results not only confirm the high potential of the HFG thickness scaling down to 4 nm with improved program performance, but also show excellent post cycling data retention and P/E cycling endurance. The optimized ultra-thin HFG planar cells show potential for manufacturability and scalability for high density memory application.

O 2 post deposition anneal of Al 2 O 3 blocking dielectric for higher performance and reliability of TANOS Flash memory

TANOS Charge Trap Flash approach (CTF) is a candidate to replace Floating Gate approach (FG) for sub-32 nm technology node. However the main challenge for TANOS is its poor retention characteristics. In this paper, we show that by performing an O2 anneal after Al2O3 deposition the charge retention is considerably improved as well as the other memory characteristics: program, erase, endurance.