S. Aur

A 0.10 /spl mu/m gate length CMOS technology with 30 /spl Aring/ gate dielectric for 1.0 V-1.5 V applications

High performance 0.1 /spl mu/m (physical) gate length CMOS with 30 /spl Aring/ gate dielectric (C-V: gate accumulated at V/sub gb/=-3 V) is demonstrated at 1.0 V-1.5 V. Scaling to 0.1 /spl mu/m L/sub gate/ CMOS is described. At 1.5 V, nMOS strong and nominal I/sub drive/=757 and 700 /spl mu/A//spl mu/m, and pMOS strong and nominal I/sub drive/=337 and 300 /spl mu/A//spl mu/m. For high performance at 1.0 V, n- and pMOS are designed with low V/sub T/ and higher I/sub off/ (100 nA//spl mu/m at L/sub g//sup min/). At 1 V, nMOS strong and nominal I/sub drive/ is 516 and 473 /spl mu/A//spl mu/m; pMOS strong and nominal I/sub drive/ is 220 and 188 /spl mu/A//spl mu/m. Benchmarking to FOM and CV/I metrics is performed for this 1.0-1.5 V, 0.1 /spl mu/m node and prior 1.8-1.5 V, 0.18 /spl mu/m nodes. Present 1.5 V, 0.1 /spl mu/m CMOS (as well as our recently reported 1.8-1.5 V, 0.18 /spl mu/m CMOS) has FOM and CV/I values better than the literature trend. The FOM at V/sub DD/=1.0 V (max I/sub off/=100 nA//spl mu/m) is the same as the 1.5 V FOM (max I/sub off/=1 nA//spl mu/m).

Antenna device reliability for ULSI processing

In this paper we assess gate oxide thickness (t/sub OX/) scaling issues with respect to key plasma processes-metal etch, contact etch and deposition, and relate the scaling trends to the mechanism of damage involved. We show that for electron shading effect, the damage effects peak for gate oxide around 30 /spl Aring/-40 /spl Aring/. We propose an antenna array scheme for plasma damage detection at small antenna ratios. We show that the local substrate potential can have a significant impact on device damage. Channel hot carrier (CHC) stress lifetime for antenna devices (both nMOSFET and pMOSFET) degrade with 2-10/spl times/ decrease in lifetime for 10/spl times/ increase in post-plasma stress Ig. Diode protection schemes are shown to be effective for 21 /spl Aring/-32 /spl Aring/ FETs.

A 1.2V, sub-0.09 /spl mu/m gate length CMOS technology

CMOS technology for 1.2 V high performance applications is being scaled to sub-0.09 /spl mu/m physical nominal gate lengths and with effective gate dielectric thickness less than 2 nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09 /spl mu/m (post gate reoxidation), and gate dielectric thickness of 2.7 nm (nMOS), 3.0 nm (pMOS) (inversion at 1.2 V), nMOS and pMOS I/sub drive/ is 763 /spl mu/A//spl mu/m and 333 /spl mu/A//spl mu/m respectively, at 1.2 V with maximum I/sub off/=5 nA//spl mu/m. Gate-drain overlap in this work is /spl sim/210 /spl Aring//side and bottomwall junction capacitance is reduced to 0.8 fF//spl mu/m/sup 2/ (pMOS) and 1.1 fF//spl mu/m/sup 2/ (nMOS). With reduced parasitics and high drive current, the 1.2 V technology FOM (Figure-of-Merit) is >39 GHz, meeting the roadmap trend.

A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issues

CMOS technology is being scaled to sub-0.1 /spl mu/m gate length and to power supply (V/sub dd/) of 1.2 V for applications of high density at lower active power than achievable with a 1.5 V-1.8 V CMOS. Many challenges are observed at this technology node including choice of gate dielectric for applications with sub-2.5 nm physical SiO/sub 2/ gate dielectric (or electrical equivalent), and maintaining roadmap performance at 1.2 V, which will require an increase in maximum off current. In this work, the nitrided gate dielectric is formed by Remote-Plasma Nitridation (RPN) of an initial thick and thus, manufacturable, physical SiO/sub 2/ layer /spl sim/3.0 nm, to achieve a final effective physical dielectric thickness /spl les/2.5 nm. In this work, for an effective t/sub ox/(acc)=3.0 nm (corresponding to /spl sim/2.5 nm effective physical Si0/sub 2/ dielectric), nMOS and pMOS nominal I/sub drive/ is 532-55 /spl mu//spl Aring///spl mu/m and 230-240 /spl mu//spl Aring///spl mu/m, respectively, at 1.2 V, with max. I/sub off/=5-10 nA//spl mu/m, With an increase in maximum I/sub off/ from 1 nA//spl mu/m (previous work) to e.g. 5 nA//spl mu/m, the 1.2 V FOM is within 3% of the target figure-of-merit specification. Nonetheless, for scaled 1.2 V technology, the effective physical gate dielectric thickness will be required to be reduced to <2.5 nm for sufficient I/sub drive/ to meet high performance requirements.

High density plasma etch induced damage to thin gate oxide

We report here severe charging caused by an inductively coupled plasma (ICP) etch, a high density plasma tool, on devices targeted for the 0.35 /spl mu/m technology mode. For the first time, direct evidence of a bi-directional charging mechanism is provided. Differential amplifiers connected to antennae exhibit offset voltage increase up to 300 mV. The lifetime of a nominal device in the presence of ICP charging is shown to reduce by a decade. Reported here for the first time is the immunity of SOI devices to such severe charging environments.

A sub-0.1 /spl mu/m gate length CMOS technology for high performance (1.5 V) and low power (1.0 V)

A high performance 1.5 V, sub-0.18 /spl mu/m (physical) gate length CMOS technology and extension to a 1.0 V technology for low power applications is described. nMOS with nominal I/sub drive/=740, 580, and 380 /spl mu/m are achieved for V/sub DD/=1.8, 1.5, and 1.0 V at accumulation t/sub ox/=36 A (from C-V at V/sub gb/=-3 V). pMOS with nominal I/sub drive/ of 300 (1.8 V), 222 (1.5 V), and 140 /spl mu/A//spl mu/m (1.0 V) are achieved. Target L/sub g//sup min/ (minimum gate length)=0.15-0.16 /spl mu/m. Drive currents are comparable to a recently reported 0.08 /spl mu/m CMOS process. Low nMOS R/sub SD/<220 /spl Omega/-/spl mu/m and pMOS R/sub SD/<500 /spl Omega/-/spl mu/m are achieved. Improvements to 1.5 V CMOS include CoSi/sub 2/ cladding, pocket implant for n- and pMOS, increased HDD and S/D dose with increased anneal, and low temperature backend processing <700/spl deg/C. Scaling of the 1.5 V CMOS to 1.0 V CMOS is achieved by (a) reduction of V/sub T/ implant dose or (b) use of shallow channel counterdoping (CD) if the V/sub T/ dose cannot be reduced further. With reduced V/sub T/ dose, nominal V/sub T//sup sat/ is reduced from 0.25 V (1.5 V CMOS) to 0.10 V (1.0 V CMOS) with small short-channel effect (SCE) for both designs. With CD and same pocket process from 1.5 V CMOS, low V/sub T/ devices are achieved with lower and constant V/sub t//sup sat/=0.06 V from L/sub gate/=0.25-0.25 /spl mu/m and with low SCE. Inverter chain delay of 37 psec for the 1.0 V, 36 A, 0.18 /spl mu/m CMOS is reduced 40% compared to a prior 1.0 V, 48 A, 0.25 /spl mu/m process.

Analog integration in a 0.35 /spl mu/m Cu metal pitch, 0.1 /spl mu/m gate length, low-power digital CMOS technology

This paper describes the integration of active and passive components to enable embedding analog circuits in an advanced digital CMOS technology developed for low standby power integrated circuits. Device design issues, device characteristics, and technology scaling are discussed in this context. The components include 1.5 V digital core CMOS, 1.5 V analog and 3.3 V I/O MOSFETs. In addition to these self-aligned MOSFETs we describe drain-extended transistors, DEnMOS and DEpMOS, where the drain extensions are formed using the well implants. A novel structure to improve the substrate collector, vertical pnp bipolar transistor is presented. The passive components described here are the n-poly on n-well capacitors and a polysilicon resistor with a low temperature coefficient of resistance, usually referred to as the zero-TCR resistor. The analog integration adds one extra mask used to block silicidation of the zero-TCR polysilicon resistor.

Utilization of plasma hydrogenation in stacked SRAM's with poly-Si PMOSFET's and bulk-Si NMOSFET's

Poly-si PMOSFETs were utilized with bulk-Si NMOSFETs in stacked SRAM cells. Results regarding utilization of a plasma hydrogenation step in a stacked SRAM process sequence are reported. It is found that poly-Si PMOSFETs exhibit an increase in ON/OFF current ratio of four orders of magnitude. Bulk-Si NMOSFETs subjected to the same hydrogenation process exhibit no significant decrease in device lifetime or significant degradation in I-V characteristics compared to NMOSFETs which were not subjected to the plasma hydrogenation process. These results indicate that plasma hydrogenation can successfully be utilized to obtain improved performance stacked SRAMs.<<ETX>>

A study of design/process dependence of 0.25 /spl mu/m gate length CMOS

We investigate the design/process dependence of a 0.25 /spl mu/m gate length CMOS technology and evaluate performance (including I/sub drive/ vs. I/sub off/, I/sub drive/ at the onset of subthreshold 2/sup nd/ slope, inverse-short-channel effect) and reliability (channel hot electron lifetime, gate-induced drain leakage, and ESD related thermal, or 2/sup nd/ breakdown). Increased nMOS I/sub drive/ before onset of subthreshold 2/sup nd/ slope (resulting from sub-surface S/D punch-through) is realized with increased As S/D anneal temperature and is correlated with reduced inverse-short-channel effect (i-SCE: measure of increase in V/sub T/ with decreasing L/sub gate/). Improved nMOS I/sub drive/ vs. I/sub off/ is additionally achieved (at same R/sub SD/) using S/D with As only compared to P LDD and is correlated with reduced sub-surface punch-through. Use of RTA annealing to 1000/spl deg/C reduces i-SCE for non-LDD nMOS as well as increasing pMOS C/sub invC/sub ox/ to /spl ges/90% at t/sub ox/=50 /spl Aring/. (comparable to nMOSFET). nMOS ESD reliability (as measured by I/sub t2/: drain current at ESD related 2/sup nd/ breakdown) is increased with optimum S/D anneal and with As only S/D. nMOS pocket implant reduces V/sub T/ rolloff and maintains hot carrier reliability and I/sub t2/ while marginally increasing C/sub j/. Use of nMOS pocket implant and pMOS super-steep retrograde channel implant improve the V/sub T/ rolloff but do not show significant improvement in I/sub drive/ vs. I/sub off/. A design/process has been implemented which results in a high performance CMOS technology consistent with industry trend as measured using a figure-of-merit metric.<<ETX>>

Failure in CMOS circuits induced by hot carriers in multi-gate transistors

The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is analyzed. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multi-gate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward biases the source junctions, causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures may occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed.<<ETX>>