A.O. Aggarwal

Copper interconnections for high performance and fine pitch flip chip digital applications and ultra-miniaturized RF module applications

Copper is an excellent candidate material for next generation of chip-package interconnections because of its high electrical and thermal conductivities, good mechanical properties at assembly and operating temperatures and well-established infrastructure to integrate with back-end processes with electroplating technology downscalable to nanoscale. This technology can also accommodate the increasing I/O density of future microprocessors with the best electrical and mechanical performance. In addition, embedment of active components with chip-last approach being proposed by Georgia Tech PRC can also be realized with the shortest interconnections resulting in performance and miniaturization comparable to chip-first approach. There is an increasing trend to replace solders with copper because of these advantages. In this paper, we describe the current status of copper bumping and copper interconnection and assembly technologies and show our future strategy

High aspect ratio metal-polymer composite structures for nano interconnects

This paper presents a novel low-temperature process that combines high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. These structures are evaluated as IC-package interconnects that can lead to reliable, low-cost and high-performance nano wafer-level packaging. High-aspect-ratio low CTE polyimide structures with low stress, high toughness and strength were fabricated using plasma etching, This dry etching process was tuned to yield a wall angle above 80 degrees leading to an aspect ratio higher than 4. The etching process also leads to roughened sidewalls for selective electroless plating on the sidewalls of the polymer structures. Simulations of these fabricated structures show tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging.

New paradigm in IC package interconnections by reworkable nano-interconnects

We propose new IC packaging technologies that have the potential to bring about disruptive innovations in interconnect pitch, best electrical and mechanical properties, low-cost and chip size. Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. Solution-derived materials for reworkable nano-interconnects can be a viable technology to meet these two challenges. Nano-grained electroplated copper is chosen as the primary interconnect material. Compliancy was addressed by tuning the process to electroplate high-aspect-ratio structures. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. Two approaches, sol-gel and electroless plating were used in this work to deposit these liquid interface films of lead free solders of the order of 50-300 nm. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 300/spl deg/C to form lead-free solders (Sn-Ag-Cu). In the other approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at temperatures of 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation. Lead-free solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive low-cost method for bump-less nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.

Design and fabrication of high aspect ratio fine pitch interconnects for wafer level packaging

The Packaging Research Center (PRC) at Georgia Tech has been exploring and evaluating novel compliant nano interconnect designs to enable high density I/O architecture for the next generation chip assembly. Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. We propose high aspect ratio interconnects as a solution that can support both electrical and mechanical requirements. The fabrication of these interconnects is similar to the standard IC fabrication and involves only one additional step beyond the standard CMOS wafer processing, thus making it a cost effective wafer level process. Extensive modeling was carried out to design 40 /spl mu/m pitch interconnects with optimized electrical and mechanical properties. The fabrication of fine-pitch copper interconnects with aspect ratio of 1:5 was demonstrated as a low-cost wafer level process. Results show that these interconnects provide the optimal combination of electrical and mechanical requirements and hence provides a viable solution for next-generation electronic packaging that can support extremely high I/O density.

50 Micron Pitch Wafer Level Packaging Testbed with Reworkable IC-Package Nano Interconnects

The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/Os in order to increase its functionality. Being able to provide several fold increase in the chip-to-package vertical interconnect density is essential for garnering the true benefits of nanotechnology that will utilize nanoscale devices. This will spur greater interest in developing electronic packages with fine and ultra fine pitches (20-50 microns). Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off in properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. We propose reworkable nano interconnects as a new interconnect paradigm for potential low cost, highest performance and reliability—not trading one for the other. This paper describes the design and fabrication of the first 50 micron pitch wafer level packaging test bed to demonstrate reworkable nano-interconnects. Nano-grained electroplated copper is chosen as the primary interconnect material. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. The processing approaches for the electroplated Cu interconnect, Sn-Cu interface and the high-density substrate wiring are presented along with the simulated mechanical and electrical performance of the interconnects.

Reliability of Nano-Structured Nickel Interconnections Replacing FlipChip Solder Assembly without Underfill

This paper reports the reliability of fine pitch interconnections using nano-structured nickel as the primary interconnection material. Assembly was accomplished with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu were used for solder-based assembly of nanonickel interconnections. Low modulus conductive adhesives impart lower stresses in the interconnections and enhance reliability though they add electrical parasitics. These were used as an alternate bonding route and compared to solders. Test vehicles were fabricated at 200 micron pitch to evaluate the reliability with different bonding routes. Different CTE substrates - FR4 with 18 ppm/C, advanced organic boards with 10 ppm/C, novel low CTE (3 ppm/C) substrates based on carbon-silicon carbide (C-SiC) were evaluated. No underfilling was used in all the test vehicles evaluated in this study. High frequency electrical characterization was performed to compare the electrical parasitics from different bonding routes. Nanometal bumps bonded with conductive adhesives showed the highest reliability withstanding 1500 cycles. This technology can be easily downscaled to submicron and nanoscale unlike the current solder technologies leading to true nanointerconnections.

Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects

The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/Os in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 microns). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This work presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress MEMS structures for extremely fine pitch wafer level packages. Finite element analysis of these structures shows tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Low CTE polyimide structures with ultra-low stress, high toughness and strength were fabricated using plasma etching. This dry etching process was tuned to yield a wall angle above 80 degrees. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. This work also describes a material solution synthesis route to develop reworkable nano-dimensional interfaces for IC-package bonding. Reworkability is addressed by a thin (200 nm) interface of lead-free high-strength solders using selective electroless plating. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation and was characterized using SEM, XRD and XPS. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate.

Thermomechanical Reliability of Nickel Pillar Interconnections Replacing Flip-Chip Solder Without Underfill

Interconnect technologies between ICs and packages or boards have a significant impact on the IC performance and packaging density. Today, the interconnections are typically accomplished with either wire bonding or flip-chip solders. While both of these technologies are incremental, they also run into either electrical or mechanical barriers as they are extended to higher density of interconnections. Downscaling traditional solder bump interconnect might not satisfy the thermomechanical reliability requirements at very fine-pitches. Alternate interconnection approaches such as compliant interconnects typically require lengthy connections and are therefore limited in terms of electrical properties, although expected to meet the mechanical requirements. This paper reports fine-pitch interconnection technologies using nano-structured nickel as primary interconnection material. The nano-grained nickels are produced by electroplating process. The primary nano-structured interconnects are assembled with different bonding methods to provide organic compatible low-temperature fabrication. Au-Sn and Sn-Cu are used for solder-based assembly of nano-nickel interconnections. Low modulus anisotropic conductive films (ACFs) are also used as an alternate bonding route of the solders. No underfilling is used in all the interconnect structures evaluated in this paper. Assembly are accomplished on different coefficient of thermal expansion (CTE) substrates including FR-4 with 18 ppm/degC, advanced organic substrates with 10 ppm/degC, novel low CTE (3 ppm/degC) substrates based on carbon-silicon carbide (C-SiC). The thermomechanical reliability of all the nano-interconnects assembled on different CTE substrates with different bonding approaches is evaluated by thermal shock testing and finite-element analysis. Nano-nickel interconnects bonded with the ACF showed the highest reliability withstanding 1500 cycles. In all cases, no apparent failure was observed in the primary nano-nickel metal interconnects. This technology is expected to be easily downscaled to submicrometer and nano-scale unlike the current solder technologies leading to true nano-interconnections.

MEMS composite structures for tunable capacitors and IC-package nano interconnects

This paper presents novel low-temperature processes that combine high-aspect-ratio polymer structures with electroless copper plating to create laterally compliant MEMS structures. This low-cost processing was developed for two applications: 1) low-voltage comb-drive actuators for tunable capacitors to reduce the tuning voltage in MEMS structures to less than 5 V and simultaneously increase the capacitance in between the electrode fingers; 2) compliant IC-package interconnects for reliable, low-cost and high-performance nano wafer-level packaging. In both situations, metallic structures show limited electrical performance and create severe reliability issues. Analytical modeling was used to show the advantages of novel composite structures. High-aspect ratio structures were fabricated from lithography and plasma etching. Processing of metal-coated polymers is limited by side-wall adhesion of metal to the polymer and polymer adhesion to underlying substrates. While photodefinable polymers can simplify the processing cost, a dry plasma etching process can give more flexibility in the selection of polymers.

Ultra-high density board technology for sub-100 /spl mu/m pitch nano-wafer level packaging

As microsystems continue to move towards higher speed and microminiaturization, the demand for interconnection density both on the IC and the package increases tremendously. With the shift towards nano ICs by 2004 with <100 nm feature sizes, the area array I/O pitch will move towards 20-100 micron in the future. The 2002 ITRS Roadmap Update identifies the need to support sub-100 /spl mu/m pitch flip-chip/WLP and data rates of 10Gbps in the package and board by the year 2010. The PRC and IME/NUS are developing 20-100 /spl mu/m pitch interconnects as part of the A*STAR nano-WLP program. A critical part of this development involves board technology to simultaneously support wiring density to direct attach of these WLPs and high speed signals. The choice of base substrate and thin film dielectric is critical to meet the electrical performance targets and achieve reliable assembly of fine pitch WLPs. Modeling revealed that a low CTE substrate greatly enhances the reliability of all the interconnect solutions being pursued. The fabrication process was done on 300 mm /spl times/ 300 mm and 300 mm /spl times/ 450 mm panel sizes using state-of-the-art printed wiring board and microvia processes. Data rates of 5Gbps on board have been demonstrated for line lengths of 10 cm using A-PPE dielectric. Fine pitch routing using 20 /spl mu/m lines and spaces on Hitachi E-679F low CTE laminate to support 200 /spl mu/m pitch pads have been demonstrated. Initial substrates for 100 /spl mu/m pitch have also been designed and fabricated.