Michael D. Sacks

New paradigm in IC package interconnections by reworkable nano-interconnects

We propose new IC packaging technologies that have the potential to bring about disruptive innovations in interconnect pitch, best electrical and mechanical properties, low-cost and chip size. Current approaches for chip to package interconnections are limited in terms of either pitch or electrical-mechanical trade-off properties. For example, lead free solder interconnects fail mechanically as the pitch is brought down from current 200 micron pitch to 20 micron. Compliant leads, on the other hand, solve mechanical reliability but at the expense of electrical performance. Solution-derived materials for reworkable nano-interconnects can be a viable technology to meet these two challenges. Nano-grained electroplated copper is chosen as the primary interconnect material. Compliancy was addressed by tuning the process to electroplate high-aspect-ratio structures. Reworkability was addressed by a thin, liquid lead-free solder interface between the interconnect and the package. Two approaches, sol-gel and electroless plating were used in this work to deposit these liquid interface films of lead free solders of the order of 50-300 nm. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 300/spl deg/C to form lead-free solders (Sn-Ag-Cu). In the other approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at temperatures of 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation. Lead-free solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive low-cost method for bump-less nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.

Development of high-k embedded capacitors on printed wiring board using sol-gel and foil-transfer processes

Sol-gel ceramic films were fabricated for organic system-on-package compatible integral capacitor applications. The films were synthesized on Ti and Ni foils which were then transferred onto organic boards using a lamination step. SrTiO/sub 3/ and BaTiO/sub 3/ films were synthesized with capacitance as high as 700 nF/cm/sup 2/ and loss as low as 0.005. It should be noted that the high permeability of Ni (approximately 100 in bulk form) and lower conductivity compared to copper decreases the skin depth and increases the resistivity of copper. This can have a deleterious effect on Q. More studies are underway to investigate this effect.

Ultra fine-pitch wafer level packaging with reworkable composite nano-interconnects

The decrease in feature sizes of micro-electronic devices has underlined the need for higher number of I/Os in order to increase its functionality. This has spurred a great interest in developing electronic packages with fine and ultra fine pitches (20-100 microns). Most of the compliant interconnects that are currently being developed have inductance and resistance higher than desirable. This work presents a novel low-temperature fabrication process that combines polymer structures with electroless copper plating to create low stress MEMS structures for extremely fine pitch wafer level packages. Finite element analysis of these structures shows tremendous reduction in the stresses at the interfaces and superior reliability as IC-package nano interconnects. Low CTE polyimide structures with ultra-low stress, high toughness and strength were fabricated using plasma etching. This dry etching process was tuned to yield a wall angle above 80 degrees. The etching process also leads to roughened sidewalls for selective electroless copper plating on the sidewalls of polymer structures. Metal-coated polymer structures from MEMS fabrication techniques can provide low-cost high-performance solutions for wafer-level-packaging. This work also describes a material solution synthesis route to develop reworkable nano-dimensional interfaces for IC-package bonding. Reworkability is addressed by a thin (200 nm) interface of lead-free high-strength solders using selective electroless plating. Lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents at 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation and was characterized using SEM, XRD and XPS. Solder film formed from the above approach was demonstrated to bond the metal-coated polymer interconnects with the copper pads on the substrate.

Exploring the limits of low cost, organics-compatible high-k ceramic thin films for embedded decoupling applications

This paper presents four organic-compatible thin film processing techniques for embedding capacitors into organic PWBs. Hydrothermal synthesis allows integration of pure nano-grained barium titanate films with capacitance density of about 1 /spl mu/F/cm/sup 2/. Sol-gel and RF-sputtering in conjunction with a foil transfer process can be used to integrate a variety of perovskite thin films with the capacitance in the range of 200-400 nF/cm/sup 2/. Thermal oxidation of titanium foil also emerges as a viable process for integrating capacitance of 100s of nF using a foil transfer process. The dielectric properties of the films synthesized by these techniques as a function of various process parameters are presented. Observed dielectric properties like dielectric constant, leakage current and breakdown strengths have been correlated to structural defects and stoichiometry of the films.

Low-cost embedded capacitor technology with hydrothermal and sol-gel processes

Fabrication of high-k embedded capacitors on printed wiring board (PWB) is limited due to the inherent low-temperature process required for organic packaging. Current dielectrics for embedded capacitors are mostly organic with insufficient dielectric constant. Integration of high-k thin films on PWB is hindered by high processing temperature of ceramics. The goal of this work, is to develop low-cost/low-temperature, aqueous/non-aqueous based processes for embedded capacitors. Hydrothermal synthesis was used for synthesis of nanograined barium titanate films. Films synthesized at 95/spl deg/C on titanium foils yielded nanograined films (<80 nm grains) with higher capacitor yield in comparison to conventional hydrothermal films from Ti precursors or sputtered Ti. Films with capacitance of more than 1.0 pF/cm/sup 2/ and thickness of 300 nm (corresponding to a dielectric constant of above 350) were developed. Oxygen plasma treatment of hydrothermal films was found to lower the loss significantly to 0.06 from 0.28. Sol-gel technique was also explored an alternate low cost large area process for synthesis of high K low loss films. Sol-gel derived films are typically crystallized and densified at temperatures that are not compatible with organic build-up processes. This limitation has been addressed using a modified sol-gel process to deposit films on a carrier foil that was subsequently laminated onto the printed wiring board. All high-temperature processing steps required by the oxide dielectrics were performed before the embedding process. High-k barium titanate (BaTiO/sub 3/) and strontium titanate (SrTiO/sub 3/) thin film capacitors were synthesized on base-metal nickel (Ni) and titanium (Ti) foils as carrier. Rapid thermal processing (RTP) lowers the process time for the development of a well-crystallized titanate film to 3 minutes as opposed to the few hours of processing time required for conventional heat treatment. Capacitance densities ranging from /spl sim/45-700 nF/cm/sup 2/ have been achieved by varying the film thicknesses from /spl sim/250 to 900 nm and the heat treatment conditions. By following the RTP with a 1 hr heat treatment in nitrogen (N/sub 2/) atmosphere, the dielectric loss was reduced to 0.005. These sol-gel and hydrothermal films were subsequently integrated onto organic boards using conventional lamination and lithography methods, followed by low-cost wet etching.

Material synthesis routes for thin film bonding interfaces in reworkable and bumpless nano-interconnects

This work explores novel material synthesis routes towards reworkable nano-dimensional interfaces for IC-package assembly, leading to bumpless and nano interconnections. Reworkability is addressed by a thin interface of lead-free high-strength solders. Two approaches, sol-gel process and electroless plating, were used to achieve these nano-dimensional bonding interfaces. In the sol-gel process, metal-organic polymer solutions were heat-treated in a reducing atmosphere at 400/spl deg/C to form lead-free solders (Sn-Ag-Cu). In the electroless plating approach, lead-free alloy films were deposited from aqueous plating solutions consisting of suitable metal salts and reducing agents. This process was done at a temperature of 45/spl deg/C. The lead-free solder composition was controlled by altering the plating bath formulation. Solder films formed from both the above approaches were demonstrated to bond copper pads. Solution-derived nano-solder technology is an attractive low-cost method for bumpless nano-interconnects and other applications such as MEMS hermetic packaging and compliant interconnect bonding.