F. Sebaai

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an L_G of 60 nm an extrinsic g_m of 1030 μS/μm at V_ds = 0.5 V is achieved which is a 1.75× increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to D_it resulting in an SS_SAT of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm L_G devices.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Gate-all-around InGaAs nanowire FETS with peak transconductance of 2200μS/μm at 50nm Lg using a replacement Fin RMG flow

We report record results for III-V gate-all-around devices fabricated on 300mm Si wafers. A gm of 2200 μS/μm with an SSsat of 110 mV/dec is achieved for an Lg=50nm device using a newly developed gate stack interlayer material deposited by ALD. In addition it is shown that high pressure annealing can further improve device performance with an average increase in gm of 22% for a 400 °C anneal.

Implementing cubic-phase HfO 2 with κ-value ∼ 30 in low-V T replacement gate pMOS devices for improved EOT-Scaling and reliability

Higher κ-value HfO₂ (κ~30) was evaluated in replacement metal gate pMOS devices. The higher-κ was achieved by doping and anneal of the HfO₂ causing crystallization into the cubic phase. The resulting gate-stack has up to 10³ × lower gate-leakage current compared to a reference HfO₂: J_G at -1 V ~ 2 μA/cm² at EOT~9.7 Å. The better J_G - EOT-scaling, result in performance and reliability improvements when normalized to the J_G.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V_T distributions [σ(V_Tsat) ~ 29mV (PMOS), ~ 49mV (NMOS) at L_gate~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H_gate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R_gate distributions down to L_gate~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H_gate~60nm, L_gate≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO₂ post-deposition N₂-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and L g down to 36nm

We report In_0.53GaAs-channel gate-all-around FETs with channel width down to 7nm and L_g down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g_m by 25% compared to InAs S/D. A g_m of 1310 μS/μm with an SS_sat of 82mV/dec is achieved for an L_g=46nm device. At this L_g, a record I_on above 200μA/μm is obtained at I_off of 100nA/μm and V_ds=0.5V on a 300mm Si platform.

Thermal and plasma treatments for improved (sub-)1 nm equivalent oxide thickness planar and FinFET-based replacement metal gate high-k last devices and enabling a simplified scalable CMOS integration scheme

We report on aggressively scaled replacement metal gate, high-k last (RMG-HKL) planar and multi-gate fin field-effect transistor (FinFET) devices, systematically investigating the impact of post high-k deposition thermal (PDA) and plasma (SF6) treatments on device characteristics, and providing a deeper insight into underlying degradation mechanisms. We demonstrate that: 1) substantially reduced gate leakage (JG) and noise can be obtained for both type of devices with PDA and F incorporation in the gate stack by SF6, without equivalent oxide thickness (EOT) penalty; 2) SF6 enables improved mobility and reduced interface trapped charge density (Nit) down to narrower fin devices [fin width (WFin) ≥ 5 nm], mitigating the impact of fin patterning and fin sidewall crystal orientations, while allowing a simplified dual-effective work function (EWF) CMOS scheme suitable for both device architectures; 3) PDA yields smaller, in absolute values, PMOS threshold voltage |VT|, and substantially improved reliability behavior due to reduction of bulk defects.

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

Strained Germanium Gate-All-Around pMOS Device Demonstration Using Selective Wire Release Etch Prior to Replacement Metal Gate Deposition

Strained Ge p-channel gate-all-around (GAA) devices with Si-passivation are demonstrated on high-density 45-nm active pitch starting from 300-mm SiGe strain relaxed buffer wafers. While single horizontal Ge nanowire (NW) devices are demonstrated, the process flow described in this paper can be adjusted to make vertically stacked horizontal Ge NWs to increase the drive per footprint. The demonstrated short-channel devices have round Ge NWs with 9-nm diameter and are the Ge GAA devices with the smallest channel and gate dimensions (<inline-formula> <tex-math notation=LaTeX>