Naoki Kusunoki

Floating Body RAM Technology and its Scalability to 32nm Node and Beyond

Technologies and improved performance of the floating body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the floating body cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

Fully-depleted (FD) floating body cell on 55nm SOI featuring excellent logic process compatibility has been successfully developed. For the first time FD operation is reported through significant signal enlargement by negative substrate bias. Using standard salicide process and FD operation, high-density embedded memory on SOI is achievable.

Steep channel & Halo profiles utilizing boron-diffusion-barrier layers (Si:C) for 32 nm node and beyond

Si:C layers under non-doped-Si epitaxial channel (Epi-channel) produces steep channel profile for 25 nm-LG nMOSFET. Si:C layers work as the dopant-diffusion-barriers from the boron doped regions. Moreover, retrograde Halo profiles are also realized in this structure. Steep channel profiles at scaled device are confirmed, and the benefits of its profile at LG of 25 nm are discussed.

A Floating-Body Cell Fully Compatible With 90-nm CMOS Technology Node for a 128-Mb SOI DRAM and Its Scalability

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage

25-nm Gate Length nMOSFET With Steep Channel Profiles Utilizing Carbon-Doped Silicon Layers (A P-Type Dopant Confinement Layer)

Steep channel profiles of scaled transistors are a promising approach for advancing transistor generation in bulk complementary metal-oxide-semiconductor (MOS). In this paper, a carbon-doped Si (Si:C) layer under an undoped Si layer is proposed to form steep p-type channel profiles in n-channel MOS field-effect transistors (nMOSFETs) due to extremely low diffusivity of boron and indium in Si:C layers. This structure with low channel impurity improves mobility and suppresses threshold voltage (VTH) variation. Both items are essential for aggressively scaled MOSFETs with a gate length less than 25 nm. We demonstrated well-controlled, high-performance, and low VTH variability nMOSFETs with a Si:C-Si epitaxial channel structure.

A 128Mb Floating Body RAM(FBRAM) on SOI with Multi-Averaging Scheme of Dummy Cell

A 128Mbit FBRAM using the floating body cell (FBC) the size of 0.17mum² (6.24F² with F=0.165mum) was successfully fabricated and a high bit yield (~99.999%) was obtained

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology

Record-high performance 32 nm node pMOSFET with advanced Two-step recessed SiGe-S/D and stress liner technology

Two-step recessed SiGe-S/D pMOSFET [1] has been optimized with a combination of compressive stress liner. Optimization on source and drain overlap, defect control and elevated SiGe-S/D structure are discussed experimentally. As a result of the careful optimization, record high drive current of 714 muA/mum at Vdd=1.0 V, Ioff =100 nA/mum at 24 nm gate length, is demonstrated.

Insight into the S/D engineering by high-resolution imaging and precise probing of 2D-carrier profiles with scanning spreading resistance microscopy

For the first time, high-resolution carrier imaging has been carried out on (110)/(100) pFETs and nFETs with scanning spreading resistance microscopy (SSRM). The S/D of (110) pFETs shows less lateral distribution than that of (100), strongly indicating 2D-channeling effect of boron I/I. Direct evidence has been shown that As out-diffusion under NiSi made conductive paths that degrade junction leakage on (110) nFETs. The Si:C influences on S/D profiles are also directly observed. We also succeeded in a full-FIB sample-making for the first time, showing the high potential of SSRM technology for further scaled devices.

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe -source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved comparing with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451muA/mum at verbar;Vdd| of 0.9V, Ioff of 100 nA/mum (552 muA/mum at |Vdd | of 1.0V). Furthermore, by combining with Vdd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation