Akira Ide
Hitachi
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Publication
Featured researches published by Akira Ide.
custom integrated circuits conference | 1990
Takashi Akioka; Atsushi Hiraishi; Tatsumi Yamauchi; Yuji Yokoyama; Shigeru Takahashi; Masahiro Iwamura; Yutaka Kobayashi; Akira Ide; Nobuyuki Gotou; Kazunori Onozawa; Hideaki Uchida
A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>
Archive | 1988
Akira Ide; Yoshikazu Saito
Archive | 1990
Atsushi Hiraishi; Takashi Akioka; Yutaka Kobayashi; Yuji Yokoyama; Masahiro Iwamura; Tatsumi Yamauchi; Shigeru Takahashi; Hideaki Uchida; Akira Ide
Archive | 1988
Akira Ide; Koichi Motohashi; Masanori Odaka; Nobuo Tamba
Archive | 1991
Yuji Yokoyama; Takashi Akioka; Masahiro Iwamura; Atsushi Hiraishi; Yutaka Kobayashi; Tatsumi Yamauchi; Shigeru Takahashi; Nobuyuki Gotou; Akira Ide
Archive | 2014
Akira Ide; Manabu Ishimatsu; Kentaro Hara
Archive | 1994
Takashi Akioka; Masahiro Iwamura; Atsushi Hiraishi; Yuji Yokoyama; Nozomu Matsuzaki; Tatsumi Yamauchi; Yutaka Kobayashi; Nobuyuki Gotou; Akira Ide; Masahiro Yamamura; Hideaki Uchida
Archive | 1990
Masahiro Iwamura; Akira Ide
Archive | 1996
Yuji Yokoyama; Takashi Akioka; Masahiro Iwamura; Atsushi Hiraishi; Yutaka Kobayashi; Tatsumi Yamauchi; Shigeru Takahashi; Nobuyuki Gotou; Akira Ide
Archive | 1990
Takashi Akioka; Atsushi Hiraishi; Akira Ide; Masahiro Iwamura; Yutaka Kobayashi; Tatsumi Yamauchi; Yuji Yokoyama
