Atsushi Hiraishi

A 6-ns 256-kbit BiCMOS TTL SRAM

A 6-ns 64K*4-b BiCMOS, transistor-transistor logic (TTL)-I/O SRAM has been developed. Fast access time is due to the combination of innovative circuits and a double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The novel circuits include a reduced-stage BiCMOS decoder and a current-sense-type address transition detection circuit. The chip size is 4.25 mm*10 mm. Simulated internal delay time components of a critical path of the decoder are shown. Address access time is 6 ns at T/sub a/=25 degrees C, V/sub CC/=5 V with a 30 pF load connected to the common I/O node.<<ETX>>

Application of circuit-level hot-carrier reliability simulation to memory design

We have applied hot-carrier circuit-level simulation to entire circuits of a few thousand to over 12 K transistors using a simple but accurate degradation model for reliability verification of actual memory products. Previous published applications were small scale (few tens of transistors or individual circuit blocks) or for experimental purposes. By applying simulation to entire circuits, areas with worst degradation are not missed due to simulating only certain circuit blocks. Varying degradation depending upon actual products make accurate total-circuit simulation a crucial part of the early design process as technology advances into the deep sub-micron high clock rate regime.

Circuit Techniques For An 8-ns Ecl 100K Compatible 3.3v 16mb Bicmos Sram With Minimum Operation Voltage Of 2.3v

We describe new circuit techniques for an 8-11s ECL compatible 16Mb BiCMOS SRAM. This is the first reported implementation of ECL lOOK U0 compatibility with an operation voltage of less than 3.0V. We developed an ECL reference circuit that operates with a 2.3V supply voltage. A novel hierarchically divided common-emitter sense circuit reduces the delay due to long data lines to achieve a simulated address access time of 8ns under typical operating conditions.