Alexander F. Kirichenko

Superconductor Digital-RF Receiver Systems

Digital superconductor electronics has been experiencing rapid maturation with the emergence of smaller-scale, lower-cost communications applications which became the major technology drivers. These applications are primarily in the area of wireless communications, radar, and surveillance as well as in imaging and sensor systems. In these areas, the fundamental advantages of superconductivity translate into system benefits through novel Digital-RF architectures with direct digitization of wide band, high frequency radio frequency (RF) signals. At the same time the availability of relatively small 4K cryocoolers has lowered the foremost market barrier for cryogenically-cooled digital electronic systems. Recently, we have achieved a major breakthrough in the development, demonstration, and successful delivery of the cryocooled superconductor digital-RF receivers directly digitizing signals in a broad range from kilohertz to gigahertz. These essentially hybrid-technology systems combine a variety of superconductor and semiconductor technologies packaged with two-stage commercial cryocoolers: cryogenic Nb mixed-signal and digital circuits based on Rapid Single Flux Quantum (RSFQ) technology, room-temperature amplifiers, FPGA processing and control circuitry. The demonstrated cryocooled digital-RF systems are the worlds first and fastest directly digitizing receivers operating with live satellite signals in X-band and performing signal acquisition in HF to L-band at ∼30GHz clock frequencies.

Zero Static Power Dissipation Biasing of RSFQ Circuits

We present a novel, resistor-free approach to dc biasing of RSFQ circuits, known as Energy-efficient RSFQ (ERSFQ). This biasing scheme does not dissipate energy in the static (non-active) mode, and dissipates orders of magnitude less power than traditional RSFQ while operating. Using this approach, we have designed, fabricated and successfully tested at low and high speed a D flip-flop with complementary outputs and several static frequency dividers. We present the method, demonstrate experimental results, and discuss future implementations of ERSFQ.

Single flux, quantum B flip-flop and its possible applications

We are introducing a new subfamily of rapid single-flux-quantum (RSFQ) digital cells, based on a single B flip-flop template. The template can be considered as an SFQ flip-flop with up to 4 inputs and 6 outputs. Each input SFQ pulse can change the flip-flops internal state. Each output presents (in the form of SFQ pulses a specific logic function of the initial state of the cell and input signals. Simple connection of various inputs and/or outputs, combined with shortening or opening of certain branches of the template allows one to implement a variety of RSFQ cells with wide margins. Of these various RSFQ cells, we have designed and successfully tested the T1 cell (asynchronous toggle flip-flop with synchronous destructive readout), single-bit full adder, and single-bit stage of an up-down counter. Experimentally measured margins for dc power supply voltage for these circuits were /spl plusmn/24%, /spl plusmn/24%, and /spl plusmn/17%, respectively.<<ETX>>

Digital Channelizing Radio Frequency Receiver

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency (RF). Such a receiver consists of a wideband analog-to-digital converter (ADC) modulator and multiple digital channelizer units to extract different frequency bands-of-interest within the broad digitized spectrum. The single-bit oversampled data, from either a lowpass delta or bandpass delta-sigma modulator, are applied to one or more channelizers, each comprising digital in-phase and quadrature mixers and a pair of digital decimation filters. We perform channelization in two steps, the first at full ADC sampling clock frequency with rapid single flux quantum (RSFQ) digital circuits and the second at reduced (decimated) clock frequency with commercial field programmable gate array (FPGA) chips at room temperature. We have demonstrated lowpass and bandpass digital receivers by integrating an ADC modulator and a channelizer unit on the same chip at clock frequencies up to 20 GHz. These 1-cm2 single-chip digital-RF receivers contain over 10,000 Josephson junctions. The channelizing receiver approach can be extended to include multiple ADC modulators and multiple channelizer units on a multi-chip module.

Implementation of a FFT radix 2 butterfly using serial RSFQ multiplier-adders

We have designed a Decimation-in-Time (DIT) radix 2 butterfly integrated circuit. This circuit will be used to implement the 32-point Fast Fourier Transform (FFT) in a parallel data flow architecture. The radix 2 butterfly circuit uses serial RSFQ math and consists of four single bit-wide serial multipliers and eight carry-save serial adders. The circuit with 16-bit word-length employs only 3400 junctions, occupies an area of 3.8/spl times/2.0 mm/sup 2/, and dissipates less than 1.1 mW power. The multiplier is implemented using the unique RSFQ bit-clock-pipelined schema. We have successfully tested a library of serial multiply-add elements: the 8-bit multiplier at 6.3 GHz and adders with dc bias margin /spl plusmn/20%. Finally, we have demonstrated full operation of the radix 2 butterfly chip with 5-bit word length.<<ETX>>

High resolution ADC using phase modulation-demodulation architecture

We report successful demonstration of a fully operational integrated superconducting ADC system based on a phase modulation/demodulation architecture. It consists of a high-resolution ADC chip with a multiple-channel race arbiter and integrated bit-pipelined decimation filter, an interface electronics block converting the ADC output to standard ECL form at sampling rates up to 200 MHz, and a computerized test station performing data acquisition, processing and display in real time. We have demonstrated a fully functional 14-bit ADC chip with 2-channel race arbiter and 16-bit decimation filter with 1:64 decimation ratio operating at 11.2 GS/s. By using additional decimation filtering of the ADC output at room temperature we demonstrated its dynamic programmability and resolution-bandwidth tradeoff. The measured ADC performance (on effective bits) was competitive with the best semiconductor high-resolution ADCs.

Multi-Band Digital-RF Receiver

A software radio receiver that can be programmed to operate in multiple wide frequency bands is required for many communication and intelligence applications. We have designed a variety of multi-band receivers, comprising a set of band-specific analog-to-digital converters (ADCs) for direct digitization of RF bands and a digital switch matrix for band selection, in two flavors: as a single superconductor integrated circuit chip and also as a multi-chip module. In addition to the ADCs and the switch, these include a 1:16 deserializer and output drivers to facilitate transport of the digitized RF data to room temperature electronics for further processing and analysis. In the single IC flavor, up to four bandpass delta-sigma ADCs minimizing quantization noise in their respective bands were integrated on the same chip and operated at clock rates up to 20 GHz. In the multi-chip module (MCM) implementation, a 1-cm × 1-cm universal active carrier was designed to accommodate any two 2.5-mm × 2.5-mm flipped chips, each containing a single ADC front-end. This standardized approach facilitates customization of two-band ADCs by selecting from a growing library of ADC front-ends, which currently cover bands ranging from HF (0-30 MHz) to Ka-band (20-21 GHz). These Multi-band MCMs and single chip ADCs were fabricated, assembled and tested.

A superconductive multi-hit time digitizer

We are developing an all-digital, high-speed, low-power superconductive multi-hit time digitizer based on a RSFQ time-to-digital converter (TDC). The advantages of this TDC, as compared to semiconductor TDCs, include excellent single, as well as multi-hit time resolution and extremely low power dissipation. Each TDC channel consists of a 14-bit superconductive counter based on toggle flip-flops with destructive readouts, a 9-word shift register-based FIFO memory, and a parallel-to-serial converter with output driver. To facilitate external control and data interfacing of the TDC, we have been developing a VXI-bus interface. Its low-power dissipation allows the TDC to be directly integrated with cooled front-end detectors, including optical detectors, eliminating cable bandwidth limitations.

Hybrid Semiconductor-Superconductor Fast-Readout Memory for Digital RF Receivers

Results of the development of a new type of a hybrid memory for superconducting Digital-RF receivers supporting 30 Gbps memory readout speed are presented. The main feature of this memory is a combination of a high capacity room-temperature memory and a high speed on-chip superconductive cache in order to provide digital waveform templates for Digital-RF signal processing. As a room-temperature high-capacity memory with fast readout, we selected Sympuls pattern generator BMG 30 G-64 M capable of producing a 30 Gbps serial data stream of programmable pattern of 67,108,864 bits. We designed, fabricated, and tested an on-chip cache which receives high-speed template serial data from the room temperature memory and converts it into a stream of 3-bit words of template of local oscillator (LO) for digital mixer. We integrated the memory with a 1 × 3-bit digital I/Q mixer (1-bit digitized RF stream multiplied by 3-bit digital LO).

ERSFQ 4-to-16 Decoder for Energy-Efficient RAM

We designed, fabricated, and demonstrated an energy-efficient ERSFQ 4-bit decoder. The first version of the decoder is designed and fabricated using HYPRES legacy 1.0-μm four-layer 4.5-kA/cm² process. It occupies an area of 700 μm × 1800 μm, which is to be reduced to 160 μm × 400 μm once fabricated using HYPRESs RIPPLE-2 0.25-μm six-layer process. The decoder features ±13% dc bias current operating margins and below 70-aJ energy consumption per one address select operation. We report test results of the decoder and discuss its future implementation in cryogenic random access memory devices, including magnetic memory devices.