Alexandre Acovic

High-performance devices for a 0.15- mu m CMOS technology

Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.<<ETX>>

Optimized silicon-rich oxide (SRO) deposition process for 5 V only flash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO/sub 2/ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO/sub 2/ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm/sup 2/ at J=0.1 A/cm/sup 2/. The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices.<<ETX>>

Effects of X-ray irradiation on GIDL in MOSFETs

The effect of X-ray irradiation on the gate-induced drain leakage (GIDL) is shown to be mostly due to the electrostatic effect of the trapped positive charge in n-channel MOSFETs. In p-channel MOSFETs, in addition, irradiation increases the interface-state-assisted tunneling component of the GIDL. In both n- and p-channel MOSFETs, a forming gas anneal at 400 degrees C completely removes all effects of irradiation on the GIDL.<<ETX>>

Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide

Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.<<ETX>>

Boron redistribution in arsenic‐implanted silicon and short‐channel effects in metal–oxide–semiconductor field effect transistors

When a high dose of As is implanted (e.g., 25 keV, 3×1015 cm−2) into B‐doped Si and the sample is subsequently annealed at 900 °C/5 min, pronounced segregation of the B into the implanted region occurs. This creates a B‐depleted region beyond the As profile. It is demonstrated that the B segregation is driven primarily by the implantation induced damage rather than by As‐B chemical and/or by electric field effects. The B segregation is nearly complete after a relatively low temperature (≲600 °C/30 min) anneal. Two‐dimensional device simulations show that the B depletion observed here can account for ≂50 mV threshold voltage roll off (at a drain bias of 0.1 V) in a Si metal–oxide–semiconductor field effect transistor of 0.2 μm gate length.

Arsenic source and drain implant induced degradation of short-channel effects in NMOSFETs

Boron is found to segregate readily from the channel region into the arsenic implanted source/data regions during the As activation anneal. The resulting boron depletion around the source and drain locally lowers the surface potential required for inversion and contributes substantially to the V/sub T/ rolloff and drain-induced barrier lowering (DIBL) in subquarter-micrometer NMOSFETs. This boron redistribution originates from the As implantation damage in the source and drain regions.<<ETX>>