Alexey Milenin

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gmSAT of 1.3mS/μm at VDS=-0.5V and good short channel control down to 60nm gate length. Optimization of P-doping in the SiGe, optimized Si cap passivation thickness on the Ge, and improved gate wrap of the channel all improve device characteristics. The Ge FinFETs presented in this work outperform published relaxed Ge FinFET devices for the gmSAT/SSSAT benchmarking metric.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

15nm-W FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

A Low-Power HKMG CMOS Platform Compatible With Dram Node 2× and Beyond

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO2 coupled with Al2O3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10-10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

A DC-pulsed capacitively-coupled planar Langmuir probe for plasma process diagnostics and monitoring

An improvement to the RF-biased planar Langmuir probe technique proposed by Braithwaite et al (1996 Plasma Sources Sci. Technol. 5 67) is demonstrated, and applied to the case of an industrial CCP reactor. Compared with the RF-biased probe, the new technique uses dc pulses instead of RF bursts, which provides similar results but with simpler electronics. The ion fluxes determined by both techniques are compared under the same O2/Ar plasma conditions using available literature data for the RF-biased case. The data show not only the same trends but very close absolute values of ion fluxes for all studied plasma conditions after correcting for the chamber-area difference. Furthermore, the new technique has the additional benefit of providing information on the ‘electron transition region’ of the I–V curve, as well as allowing the resistance and capacitance of films deposited on the probe to be determined. Finally, both experimental data and numerical simulations of the I–V characteristics and the film parameters are presented for different oxidizing plasmas.

First demonstration of 15nm-W FIN inversion-mode relaxed-Germanium n-FinFETs with Si-cap free RMG and NiSiGe Source/Drain

This work demonstrates the feasibility of an inversion-mode relaxed Ge n-FinFET scaled down to 15-nm fin width and sub-40-nm gate length. CMOS-compatible processing steps such as STI formation, replacement metal gate (RMG), in-situ Phosphorus-doped raised-Source/Drain and a Ni-based contact scheme have been successfully implemented. This first industry-compatible Ge n-FinFET has a G_M,SAT,EXT / SS_SAT of 250 μS.μm^-1 / 130 mV.dec^-1 (at the targeted V_DS=0.5V) which is on par with accumulation-mode junction-less Ge n-FETs.

Performance and reliability of high-mobility Si 0.55 Ge 0.45 p-channel FinFETs based on epitaxial cladding of Si Fins

We present a comprehensive study of Si0.55Ge0.45-cladded p-channel FinFETs, including a comparison with planar SiGe quantum-well devices. The SiGe-cladded FinFETs exhibit ~2× higher hole mobility, ~2× better ION/IOFF, and improved DIBL compared to Si control devices. Superior NBTI reliability over equivalent Si FinFETs is demonstrated for cladding thicknesses down to 3 nm. The dependencies of drive current and hole mobility on both SiGe thickness and device width are examined in detail. This analysis shows that SiGe thickness conformality and epitaxial facet control are crucial for the optimization of SiGe-cladded FinFETs.

Strained germanium gate-all-around PMOS device demonstration using selective wire release etch prior to replacement metal gate deposition

Strained Ge p-channel Gate-All-Around (GAA) FETs are demonstrated on 300mm SiGe Strain Relaxed Buffer (SRB) and 45nm Fin pitch with the shortest gate lengths (Lg=40nm) and smallest Ge nanowire (NW) diameter (d=9nm) reported to date. Optimization of groundplane doping (GP) is required to minimize the impact of the parasitic channel in the SRB. The strained Ge GAA devices maintain excellent electrostatic control at the shortest gate lengths studied (Lg=40nm) with DIBL of 30mV/V and sub-threshold slope (SSsat) of 79mV/dec. This work shows a significant improvement not only compared to our previous work on strained Ge finFETs but also when benchmarked to published Ge GAA devices.

Seedless templated growth of hetero-nanostructures for novel microelectronics devices

The feasibility of a templated seedless approach for growing segmented p-i-n nanowires –based diodes based on selective epitaxial growth is demonstrated. Such diodes are the basic structure for a TunnelFET device. This approach has the potential for being easily scalable at a full-wafer processing, and there is no theoretical limitation for control on nanowires growth and properties when scaling down their diameters, as opposed to an unconstrained vapor-liquid-solid growth. Moreover, Si/SixGe1-x hetero-structures are implemented, showing that this can improve the TFET ON current not only thanks to the lowered barrier for the band-to-band source-channel tunneling, but additionally thanks to its lower thermal budget for growth, allowing for better control of the abruptness of the doping profile at the source-channel tunneling interface.