K. Barla

InGaAs Gate-All-Around Nanowire Devices on 300mm Si Substrates

In this letter, we present the first InGaAs gate-all-around (GAA) nanowire devices fabricated on 300mm Si substrates. For an L_G of 60 nm an extrinsic g_m of 1030 μS/μm at V_ds = 0.5 V is achieved which is a 1.75× increase compared with the replacement fin FinFet process. This improvement is attributed to the elimination of Mg counterdoping in the GAA flow. Ultrascaled nanowires with diameters of 6 nm were demonstrated to show immunity to D_it resulting in an SS_SAT of 66 mV/decade and negligible drain-induced barrier lowering for 85-nm L_G devices.

An InGaAs/InP quantum well finfet using the replacement fin process integrated in an RMG flow on 300mm Si substrates

InGaAs FinFETs fabricated by an unique Si fin replacement process have been demonstrated on 300mm Si substrates. The devices are integrated by process modules developed for a Si-IIIV hybrid 300mm R&D pilot line, compatible for future CMOS high-volume manufacturing. First devices with a SS of 190 mV/dec and extrinsic gm of 558 μS/μm are achieved for an EOT of 1.9nm, Lg of 50nm and fin width of 55nm. A trade-off between off state leakage and mobility for different p-type doping levels of the InP and InGaAs layers is found and the RMG high-κ last processing is demonstrated to offer significant performance improvements over that of high-κ first.

Strained Germanium quantum well pMOS FinFETs fabricated on in situ phosphorus-doped SiGe strain relaxed buffer layers using a replacement Fin process

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are reported for the first time, demonstrating peak transconductance gmSAT of 1.3mS/μm at VDS=-0.5V and good short channel control down to 60nm gate length. Optimization of P-doping in the SiGe, optimized Si cap passivation thickness on the Ge, and improved gate wrap of the channel all improve device characteristics. The Ge FinFETs presented in this work outperform published relaxed Ge FinFET devices for the gmSAT/SSSAT benchmarking metric.

Strained germanium quantum well p-FinFETs fabricated on 45nm Fin pitch using replacement channel, replacement metal gate and germanide-free local interconnect

Strained Ge p-channel FinFETs on Strain Relaxed SiGe are integrated for the first time on high density 45nm Fin pitch using a replacement channel approach on Si substrate. In comparison to our previous work on isolated sGe FinFETs [1], 14/16nm technology node compatible modules such as replacement metal gate and germanide-free local interconnect were implemented. The ION/IOFF benchmark shows the high density strained Ge p-FinFETs in this work outperform the best published isolated strained Ge on SiGe devices.

15nm-W FIN high-performance low-defectivity strained-germanium pFinFETs with low temperature STI-last process

An STI-last integration scheme was successfully developed to fabricate low-defectivity and dopant-controlled SiGe SRB / sGe Fins. For the first time, 15 nm fin-width SiGe SRB/highly-strained Ge pFinFETs are demonstrated down to 35 nm gate length. With a CET_INV-normalized G_M,SAT,INT of 6.7 nm.mS/μm, the Si_0.3Ge_0.7 / sGe pFinFETs presented in this work improve the performance by ~90% as compared to the state-of-the-art relaxed-Ge FinFETs.

Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

Accurate determination of contact resistivities (P_c) below 1 × 10^-8 Ω · cm² is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined TLM (RTLM) has a high Pc accuracy at the expense of a more complex fabrication. In this letter, we will present a novel model-multiring CTLM (MR-CTLM), which combines the advantages of a simple process and a high <i>Pc</i> extraction resolution. We fabricated ultralow<i>-Pc</i> Ti/n-Si contacts and demonstrated the capability of MR-CTLM to extract the P_c as low as 6.2 × 10^-9 Ω · cm² with high precision.

Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.

A Simplified Method for (Circular) Transmission Line Model Simulation and Ultralow Contact Resistivity Extraction

The metal resistance in the transmission line model (TLM) structures creates a serious obstacle to determine precisely the intrinsic contact resistivity. To tackle this problem, we propose a new model, the lump model, to evaluate the metal resistance influence in both TLM and circular TLM (CTLM) test structures. In this letter, we demonstrate the high simplicity, great robustness, and flexibility of the lump model. The previous reported contact resistivity values extracted with CTLM are usually above 1 χ 10-7Ω · cm2 because the metal resistance impact is commonly neglected. This is the first time that the role of the metal in CTLM is appropriately analyzed. Low contact resistivity, 3.6χ10-8Ω · cm2, of standard NiSi/n-Si contact has been extracted and this shows the high sensitivity of this method.

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO 2 /n-Si Contact

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height (qφb) MIS contact: Ti/TiO₂/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO₂/n-Si thermal stability study under different electron conduction mechanisms. We find that both qφ_b and contact resistivity (ρ_c) of the Ti/TiO₂/n-Si MIS contacts vary dramatically after mere 300°C-500°C 1-min rapid thermal treatments. The variations in qφ_b and ρ_c are related to the thermally driven TiO₂ decomposition. This thermal stability study of Ti/TiO₂/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive lowwork function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed.

Low-Resistance Titanium Contacts and Thermally Unstable Nickel Germanide Contacts on p-Type Germanium

Ti/p-Ge and NiGe/p-Ge contacts are compared on both planar and fin-based devices. Ti/p-Ge contacts show low contact resistance, while NiGe/p-Ge devices show short circuit problems due to thermally driven Ni diffusion. Considering the thermal budget in the standard backend of line processing for CMOS, Ti is more suitable for p-Ge devices. A low Ti/p-Ge contact resistivity of 1.1 × 10-8 Ω · cm2 is achieved by using a multi-pulse laser annealing technique for B activation.