AliReza Alian

A Combined Interface and Border Trap Model for High-Mobility Substrate Metal–Oxide–Semiconductor Devices Applied to

By taking into account simultaneously the effects of border traps and interface states, the authors model the alternating current capacitance-voltage (C-V) behavior of high-mobility substrate metal-oxide-semiconductor (MOS) capacitors. The results are validated with the experimental In0.53Ga0.47As/ high-κ and InP/high-κ (C-V) curves. The simulated C-V and conductance-voltage (G-V) curves reproduce comprehensively the experimentally measured capacitance and conductance data as a function of bias voltage and measurement frequency, over the full bias range going from accumulation to inversion and full frequency spectra from 100 Hz to 1 MHz. The interface state densities of In0.53Ga0.47As and InP MOS devices with various high-κ dielectrics, together with the corresponding border trap density inside the high-κ oxide, were derived accordingly. The derived interface state densities are consistent to those previously obtained with other measurement methods. The border traps, distributed over the thickness of the high- κ oxide, show a large peak density above the two semiconductor conduction band minima. The total density of border traps extracted is on the order of 1019 cm-3. Interface and border trap distributions for InP and In0.53Ga0.47As interfaces with high-κ oxides show remarkable similarities on an energy scale relative to the vacuum reference.

\hbox{In}_{0.53} \hbox{Ga}_{0.47}\hbox{As}

Over the last years there has been lots of interest in the use of germanium and III-V compounds as potential replacements for silicon channels. Germanium with its high hole mobility has attracted lots of attention for its application in advanced pMOS devices. Indium gallium arsenide compounds, with their intrinsically superior electron mobility and high saturation velocity, are considered as a candidate for nMOS devices beyond 14 nm node technology.

and InP Capacitors

We investigated the passivation of In0.53Ga0.47As (001) surface by molecular beam epitaxy techniques. After growth of strained In0.53Ga0.47As on InP (001) substrate, HfO2/Al2O3 high-κ oxide stacks have been deposited in-situ after surface reconstruction engineering. Excellent capacitance-voltage characteristics have been demonstrated along with low gate leakage currents. The interfacial density of states (Dit) of the Al2O3/In0.53Ga0.47As interface have been revealed by conductance measurement, indicating a downward Dit profile from the energy close to the valence band (medium 1012 cm−2eV−1) towards that close to the conduction band (1011 cm−2eV−1). The low Dit’s are in good agreement with the high Fermi-level movement efficiency of greater than 80%. Moreover, excellent scalability of the HfO2 has been demonstrated as evidenced by the good dependence of capacitance oxide thickness on the HfO2 thickness (dielectric constant of HfO2 ∼20) and the remained low Dit’s due to the thin Al2O3 passivation layer. The...

Advancing CMOS beyond the Si roadmap with Ge and III/V devices

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

Low interfacial trap density and sub-nm equivalent oxide thickness in In0.53Ga0.47As (001) metal-oxide-semiconductor devices using molecular beam deposited HfO2/Al2O3 as gate dielectrics

The integration of high carrier mobility materials into future CMOS generations is presently being studied in order to increase drive current capability and to decrease power consumption in future generation CMOS devices. If III–V materials are the candidates of choice for n-type channel devices, antimonide-based semiconductors present high hole mobility and could be used for p-type channel devices. In this work we first demonstrate the heteroepitaxy of fully relaxed GaSb epilayers on InP(001) substrates. In a second part, the properties of the Al2O3/GaSb interface have been studied by in situ deposition of an Al2O3 high-κ gate dielectric. The interface is abrupt without any substantial interfacial layer, and is characterized by high conduction and valence band offsets. Finally, MOS capacitors show well-behaved C–V with relatively low Dit along the bandgap, these results point out an efficient electrical passivation of the Al2O3/GaSb interface.

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

InGaAs channel MOSFET devices with a channel thickness down to 3nm were fabricated and systematically characterized. Thinner channels result in improved electrostatics, however, the mobility rapidly drops to 110 cm2/Vs for the 3nm thick channel which results in significant loss of the drive current. 10 nm was found to be the optimum channel thickness with 77 mV/dec sub-threshold swing (SS). To account for the band-mixing and nonparabolicity of the III-V systems, 8-bands k.p simulations were conducted to gain an accurate insight into the device operation. As also verified experimentally, simulations suggest that the accumulation capacitance value increases as the channel thickness decreases due to the variations in the inversion charge profile. Simulations suggest that the InP buffer response affects the effective mass of the carriers and reduces the mobility as the channel becomes thinner. Based on this work, InGaAs channel thicknesses of 5nm and below hit severe performance issues.

GaSb molecular beam epitaxial growth on p-InP(001) and passivation with in situ deposited Al2O3 gate oxide

High-Mobility n-MOSFET options with Ge and InGaAs channels are of intense interests. As the well-known interfacial trap (Dit) problem appears now contained, new challenges are emerging from above the interface. The evidence of oxide border traps (BT) in high-k dielectrics and its effect on the on-state performance of Ge and InGaAs n-MOSFETs are presented in this study through combined trap and transport analyses. The impact of the oxide traps on device frequency response and threshold voltage (Vth) stability could challenge the commercial realization of the high mobility channel MOSFET.

Impact of the channel thickness on the performance of ultrathin InGaAs channel MOSFET devices

We introduce an ac transconductance dispersion method (ACGD) to profile the oxide traps in an MOSFET without needing a body contact. The method extracts the spatial distribution of oxide traps from the frequency dependence of transconductance, which is attributed to charge trapping as modulated by an ac gate voltage. The results from this method have been verified by the use of the multifrequency charge pumping (MFCP) technique. In fact, this method complements the MFCP technique in terms of the trap depth that each method is capable of probing. We will demonstrate the method with InP passivated InGaAs substrates, along with electrically stressed Si N-MOSFETs.

Beyond interface: The impact of oxide border traps on InGaAs and Ge n-MOSFETs

The efficiency of the ammonium sulfide vapor (ASV) treatment, as opposed to the wet treatment in the liquid ammonium sulfide solution, on the performance improvement of the In0.53Ga0.47As surface-channel as well as InP-capped buried-channel metal-oxide-semiconductor field-effect-transistors (MOSFET) was demonstrated for the first time. MOSFETs were fabricated with either HCl or ASV surface treatments prior to the gate oxide deposition. ASV treatment was found to be very efficient in boosting the drive current of the transistors compared to that of the HCl treatment. It was also found that the ASV treatment leads to a lower border trap density and slightly higher oxide/semiconductor interface defect density compared to that of the HCl treatment. X-ray photoelectron spectroscopy (XPS) studies of In0.53Ga0.47As native oxide regrowth after both surface treatments identified indium sub-oxides as a possible cause of the performance degradation of the HCl treated devices. Based on this work, ASV treatment could ...

AC Transconductance Dispersion (ACGD): A Method to Profile Oxide Traps in MOSFETs Without Body Contact

Trap spectroscopy by charge injection and sensing method was applied to the In_0.53Ga_0.47As-Al₂O₃ system, yielding the spatial and energetic distribution of the traps inside the Al₂O₃ layer. The trap density inside the atomic-layer-deposited (ALD) Al₂O₃ layer was found to be significantly reduced by (NH₄)₂S treatment of the InGaAs surface prior to the Al₂O₃ deposition. Indium concentration inside the Al₂O₃ layer was found to be reduced once the InGaAs surface is (NH₄)₂S treated prior to the Al₂O₃ deposition as measured by time-of-flight secondary ion mass spectroscopy, indicating indium as a possible origin of the oxide traps. The results suggest a new mechanism for the sulfur action at the InGaAs surface, which might be responsible for the transistor performance improvements observed after ( NH₄)₂S passivation. This mechanism involves sulfur as an indium diffusion/segregation barrier stabilizing the InGaAs surface during the ALD Al₂O₃ deposition, lowering the oxide trap density. This, in turn, improves the electron mobility through a reduction in the Coulomb scattering of the carriers due to border traps and improves the device drive current.